changeset 0cce97fe6390 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0cce97fe6390
description:
inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
diffstat:
src/arch/alpha/tlb.cc | 2 +-
src/cpu/inorder/resources/cache_unit.cc | 11 +++++++++--
2 files changed, 10 insertions(+), 3 deletions(-)
diffs (34 lines):
diff -r 1edf525495b1 -r 0cce97fe6390 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Sun Jun 19 21:43:41 2011 -0400
+++ b/src/arch/alpha/tlb.cc Sun Jun 19 21:43:41 2011 -0400
@@ -457,7 +457,7 @@
return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
}
- if (PcPAL(tc->pcState().pc())) {
+ if (PcPAL(req->getPC())) {
mode = (req->getFlags() & Request::ALTMODE) ?
(mode_type)ALT_MODE_AM(
tc->readMiscRegNoEffect(IPR_ALT_MODE))
diff -r 1edf525495b1 -r 0cce97fe6390 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Sun Jun 19 21:43:41 2011 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc Sun Jun 19 21:43:41 2011 -0400
@@ -426,9 +426,16 @@
ThreadID tid = inst->readTid();
setupMemRequest(inst, cache_req, acc_size, flags);
+
+ //@todo: HACK: the DTB expects the correct PC in the ThreadContext
+ // but how if the memory accesses are speculative? Shouldn't
+ // we send along the requestor's PC to the translate functions?
+ ThreadContext *tc = cpu->thread[tid]->getTC();
+ PCState old_pc = tc->pcState();
+ tc->pcState() = inst->pcState();
inst->fault =
- _tlb->translateAtomic(cache_req->memReq,
- cpu->thread[tid]->getTC(), tlb_mode);
+ _tlb->translateAtomic(cache_req->memReq, tc, tlb_mode);
+ tc->pcState() = old_pc;
if (inst->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
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