[gem5-dev] changeset in gem5: inorder: clear fetchbuffer on traps

[Korey Sewell]

changeset 80aa16801996 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=80aa16801996
description:
        inorder: clear fetchbuffer on traps
        implement clearfetchbufferfunction
        extend predecoder to use multiple threads and clear those on trap

diffstat:

 src/cpu/inorder/resources/fetch_unit.cc |  44 +++++++++++++++++++++++++++------
 src/cpu/inorder/resources/fetch_unit.hh |   4 ++-
 2 files changed, 39 insertions(+), 9 deletions(-)

diffs (91 lines):

diff -r b5d3e3d05173 -r 80aa16801996 src/cpu/inorder/resources/fetch_unit.cc
--- a/src/cpu/inorder/resources/fetch_unit.cc   Sun Jun 19 21:43:41 2011 -0400
+++ b/src/cpu/inorder/resources/fetch_unit.cc   Sun Jun 19 21:43:41 2011 -0400
@@ -57,9 +57,11 @@
                      int res_latency, InOrderCPU *_cpu,
                      ThePipeline::Params *params)
     : CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
-      instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize),
-      predecoder(NULL)
-{ }
+      instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
+{
+    for (int tid = 0; tid < MaxThreads; tid++)
+        predecoder[tid] = new Predecoder(NULL);
+}
 
 FetchUnit::~FetchUnit()
 {
@@ -109,10 +111,10 @@
     MachInst mach_inst =
         TheISA::gtoh(fetchInsts[fetch_offset]);
 
-    predecoder.setTC(cpu->thread[tid]->getTC());
-    predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
-    assert(predecoder.extMachInstReady());
-    ext_inst = predecoder.getExtMachInst(instPC);
+    predecoder[tid]->setTC(cpu->thread[tid]->getTC());
+    predecoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
+    assert(predecoder[tid]->extMachInstReady());
+    ext_inst = predecoder[tid]->getExtMachInst(instPC);
 
     inst->pcState(instPC);
     inst->setMachInst(ext_inst);
@@ -231,6 +233,22 @@
 }
 
 void
+FetchUnit::clearFetchBuffer()
+{
+    std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
+    std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
+
+    while (fetch_it != end_it) {
+        if ((*fetch_it)->block) {
+            delete [] (*fetch_it)->block;
+        }
+        delete *fetch_it;
+        fetch_it++;
+    }
+    fetchBuffer.clear();
+}
+
+void
 FetchUnit::execute(int slot_num)
 {
     CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(reqs[slot_num]);
@@ -563,5 +581,15 @@
 FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 {
     //@todo: per thread?
-    predecoder.reset();
+    predecoder[tid]->reset();
+
+    //@todo: squash using dummy inst seq num
+    squash(NULL, NumStages - 1, 0, tid);
+
+    //@todo: make sure no blocks are in use
+    assert(blocksInUse() == 0);
+    assert(pendingFetch.size() == 0);
+
+    //@todo: clear pendingFetch and fetchBuffer
+    clearFetchBuffer();
 }
diff -r b5d3e3d05173 -r 80aa16801996 src/cpu/inorder/resources/fetch_unit.hh
--- a/src/cpu/inorder/resources/fetch_unit.hh   Sun Jun 19 21:43:41 2011 -0400
+++ b/src/cpu/inorder/resources/fetch_unit.hh   Sun Jun 19 21:43:41 2011 -0400
@@ -120,11 +120,13 @@
 
     int blocksInUse();
 
+    void clearFetchBuffer();
+
     int instSize;
 
     int fetchBuffSize;
 
-    TheISA::Predecoder predecoder;
+    TheISA::Predecoder *predecoder[ThePipeline::MaxThreads];
 
     /** Valid Cache Blocks*/
     std::list<FetchBlock*> fetchBuffer;
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev