changeset 020248dd406f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=020248dd406f
description:
alpha:o3:simple: update simout/err files
A few prior changesets have changed the gem5 output in a way that wont
cause
errors but may be confusing for someone trying to debug the
regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning
Additionaly, the last updated stats changes rearrange the ordering of
the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All
the regressions pass
w/the same stats even though it looks like they are being changed.
diffstat:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr | 11 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout | 16 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 856 ++++----
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr | 11 +-
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout | 16 +-
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt | 98 +-
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr | 11 +-
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout | 16 +-
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt | 458 ++--
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr | 12 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout | 16 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 856 ++++----
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr | 12 +-
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout | 16 +-
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt | 98 +-
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr | 12 +-
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout | 16 +-
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt | 458 ++--
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr | 11 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout | 16 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 856 ++++----
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr | 11 +-
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout | 16 +-
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt | 98 +-
tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr | 11 +-
tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout | 16 +-
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt | 458 ++--
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr | 11 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 16 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 872 +++++-----
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr | 11 +-
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout | 16 +-
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt | 98 +-
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr | 11 +-
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout | 16 +-
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt | 458 ++--
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr | 11 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout | 16 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 854 ++++----
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr | 11 +-
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout | 16 +-
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt | 98 +-
tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr | 11 +-
tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout | 16 +-
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt | 458 ++--
tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr | 1 -
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout | 16 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 854 ++++----
tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr | 1 -
tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout | 16 +-
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt | 98 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr | 1 -
tests/quick/00.hello/ref/alpha/linux/simple-timing/simout | 16 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt | 450 ++--
tests/quick/00.hello/ref/mips/linux/o3-timing/simerr | 1 -
tests/quick/00.hello/ref/mips/linux/o3-timing/simout | 16 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 820 ++++----
57 files changed, 4807 insertions(+), 4965 deletions(-)
diffs (truncated from 10641 to 300 lines):
diff -r d9f54de93703 -r 020248dd406f
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr Mon Jun 20
02:29:14 2011 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr Mon Jun 20
18:57:14 2011 -0400
@@ -1,11 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff -r d9f54de93703 -r 020248dd406f
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Mon Jun 20
02:29:14 2011 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Mon Jun 20
18:57:14 2011 -0400
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 21 2011 12:29:56
-M5 started Apr 21 2011 13:02:50
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
+gem5 compiled Jun 19 2011 06:59:13
+gem5 started Jun 19 2011 07:20:02
+gem5 executing on m60-009.pool
+command line: build/ALPHA_SE/gem5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff -r d9f54de93703 -r 020248dd406f
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Mon Jun 20
02:29:14 2011 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Mon Jun 20
18:57:14 2011 -0400
@@ -1,162 +1,66 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 235652 #
Simulator instruction rate (inst/s)
-host_mem_usage 207744 #
Number of bytes of host memory used
-host_seconds 2399.95 #
Real time elapsed on the host
-host_tick_rate 67644016 #
Simulator tick rate (ticks/s)
-sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 565552443 #
Number of instructions simulated
sim_seconds 0.162342 #
Number of seconds simulated
sim_ticks 162342217500 #
Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 63645886 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 71175082 #
Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 199 #
Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 4119052 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 70244988 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 76158972 #
Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1672188 #
Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts 4118243 #
The number of times a branch was mispredicted
-system.cpu.commit.branches 62547159 #
Number of branches committed
-system.cpu.commit.bw_lim_events 20370282 #
number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts 601856963 #
The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 59876142 #
The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples 315015358
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.910564
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.344745
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 102187516 32.44% 32.44% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 100337503 31.85% 64.29% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 36333939 11.53% 75.82% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9834278 3.12% 78.95% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 9585018 3.04% 81.99% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 21675104 6.88% 88.87% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 13171126 4.18% 93.05% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1520592 0.48% 93.53% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 20370282 6.47% 100.00% #
Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 315015358
# Number of insts commited each cycle
-system.cpu.commit.count 601856963 #
Number of instructions committed
-system.cpu.commit.fp_insts 1520 #
Number of committed floating point instructions.
-system.cpu.commit.function_calls 1197610 #
Number of function calls committed.
-system.cpu.commit.int_insts 563954763 #
Number of committed integer instructions.
-system.cpu.commit.loads 114514042 #
Number of loads committed
-system.cpu.commit.membars 0 #
Number of memory barriers committed
-system.cpu.commit.refs 153965363 #
Number of memory references committed
-system.cpu.commit.swp_count 0 #
Number of s/w prefetches committed
-system.cpu.committedInsts 565552443 #
Number of Instructions Simulated
-system.cpu.committedInsts_total 565552443 #
Number of Instructions Simulated
-system.cpu.cpi 0.574101 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.574101 #
CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 3 #
number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 3 #
number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 112204531 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 15171.487288
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7363.877609
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 111416977 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 11948365500 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.007019 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 787554 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 569368 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1606695000
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001945 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 218186 #
number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 39451321 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14289.032218
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11301.125107
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 38165226 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 18377052890 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.032600 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1286095 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1029147 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2903801494
# number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.006513 #
mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 256948 #
number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7344.320755
# average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 314.821095 #
Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 106 #
number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 11 #
number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 778498
# number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 224000
# number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 151655852 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 14624.181040 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 9493.104038
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 149582203 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 30325418390 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.013673 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 2073649 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 1598515 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4510496494
# number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003133 #
mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 475134 #
number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 #
number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4094.151824 #
Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999549 #
Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 151655852 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 14624.181040
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038
# average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 149582203 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 30325418390 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.013673 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 2073649 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 1598515 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4510496494
# number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003133 #
mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 475134 #
number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 471038 #
number of replacements
-system.cpu.dcache.sampled_refs 475134 #
Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.151824 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 149582206 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 126677000 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 423176 #
number of writebacks
-system.cpu.decode.BlockedCycles 44833716 #
Number of cycles decode is blocked
-system.cpu.decode.BranchMispred 844 #
Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved 4163323 #
Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts 687863087 #
Number of instructions handled by decode
-system.cpu.decode.IdleCycles 142213399 #
Number of cycles decode is idle
-system.cpu.decode.RunCycles 122593858 #
Number of cycles decode is running
-system.cpu.decode.SquashCycles 9601978 #
Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts 3402 #
Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles 5374385 #
Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 163150258 #
DTB accesses
-system.cpu.dtb.data_acv 0 #
DTB access violations
+sim_freq 1000000000000 #
Frequency of simulated ticks
+host_inst_rate 248957 #
Simulator instruction rate (inst/s)
+host_tick_rate 71463217 #
Simulator tick rate (ticks/s)
+host_mem_usage 193608 #
Number of bytes of host memory used
+host_seconds 2271.69 #
Real time elapsed on the host
+sim_insts 565552443 #
Number of instructions simulated
+system.cpu.dtb.fetch_hits 0 #
ITB hits
+system.cpu.dtb.fetch_misses 0 #
ITB misses
+system.cpu.dtb.fetch_acv 0 #
ITB acv
+system.cpu.dtb.fetch_accesses 0 #
ITB accesses
+system.cpu.dtb.read_hits 122220880 #
DTB read hits
+system.cpu.dtb.read_misses 24742 #
DTB read misses
+system.cpu.dtb.read_acv 0 #
DTB read access violations
+system.cpu.dtb.read_accesses 122245622 #
DTB read accesses
+system.cpu.dtb.write_hits 40876425 #
DTB write hits
+system.cpu.dtb.write_misses 28211 #
DTB write misses
+system.cpu.dtb.write_acv 0 #
DTB write access violations
+system.cpu.dtb.write_accesses 40904636 #
DTB write accesses
system.cpu.dtb.data_hits 163097305 #
DTB hits
system.cpu.dtb.data_misses 52953 #
DTB misses
-system.cpu.dtb.fetch_accesses 0 #
ITB accesses
-system.cpu.dtb.fetch_acv 0 #
ITB acv
-system.cpu.dtb.fetch_hits 0 #
ITB hits
-system.cpu.dtb.fetch_misses 0 #
ITB misses
-system.cpu.dtb.read_accesses 122245622 #
DTB read accesses
-system.cpu.dtb.read_acv 0 #
DTB read access violations
-system.cpu.dtb.read_hits 122220880 #
DTB read hits
-system.cpu.dtb.read_misses 24742 #
DTB read misses
-system.cpu.dtb.write_accesses 40904636 #
DTB write accesses
-system.cpu.dtb.write_acv 0 #
DTB write access violations
-system.cpu.dtb.write_hits 40876425 #
DTB write hits
-system.cpu.dtb.write_misses 28211 #
DTB write misses
+system.cpu.dtb.data_acv 0 #
DTB access violations
+system.cpu.dtb.data_accesses 163150258 #
DTB accesses
+system.cpu.itb.fetch_hits 65447834 #
ITB hits
+system.cpu.itb.fetch_misses 37 #
ITB misses
+system.cpu.itb.fetch_acv 0 #
ITB acv
+system.cpu.itb.fetch_accesses 65447871 #
ITB accesses
+system.cpu.itb.read_hits 0 #
DTB read hits
+system.cpu.itb.read_misses 0 #
DTB read misses
+system.cpu.itb.read_acv 0 #
DTB read access violations
+system.cpu.itb.read_accesses 0 #
DTB read accesses
+system.cpu.itb.write_hits 0 #
DTB write hits
+system.cpu.itb.write_misses 0 #
DTB write misses
+system.cpu.itb.write_acv 0 #
DTB write access violations
+system.cpu.itb.write_accesses 0 #
DTB write accesses
+system.cpu.itb.data_hits 0 #
DTB hits
+system.cpu.itb.data_misses 0 #
DTB misses
+system.cpu.itb.data_acv 0 #
DTB access violations
+system.cpu.itb.data_accesses 0 #
DTB accesses
+system.cpu.workload.num_syscalls 17 #
Number of system calls
+system.cpu.numCycles 324684436 #
number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
+system.cpu.BPredUnit.lookups 76158972 #
Number of BP lookups
+system.cpu.BPredUnit.condPredicted 70244988 #
Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 4119052 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 71175082 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 63645886 #
Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS 1672188 #
Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 199 #
Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 65447834 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 697103085 #
Number of instructions fetch has processed
system.cpu.fetch.Branches 76158972 #
Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 65318074 #
Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 129743678 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4139889 #
Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 37 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
system.cpu.fetch.CacheLines 65447834 #
Number of cache lines fetched
-system.cpu.fetch.Cycles 129743678 #
Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1277663 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 697103085 #
Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 37 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
-system.cpu.fetch.SquashCycles 4139889 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.234563 #
Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 65447834 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 65318074 #
Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.147017 #
Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 324617336 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.147461 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.098162 #
Number of instructions fetched each cycle (Total)
@@ -174,111 +78,98 @@
system.cpu.fetch.rateDist::min_value 0 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 324617336 #
Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads 253 #
number of floating regfile reads
-system.cpu.fp_regfile_writes 50 #
number of floating regfile writes
-system.cpu.icache.ReadReq_accesses 65447834 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36501.303215
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35511.551155
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 65446683 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 42013000 #
number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000018 #
miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1151 #
number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 242 #
number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 32280000
# number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 #
mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 909 #
number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 71998.551155 #
Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 #
number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
-system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 65447834 #
number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36501.303215 #
average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35511.551155
# average overall mshr miss latency
-system.cpu.icache.demand_hits 65446683 #
number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 42013000 #
number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000018 #
miss rate for demand accesses
-system.cpu.icache.demand_misses 1151 #
number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 242 #
number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 32280000
# number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000014 #
mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 909 #
number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 #
number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
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