I'd put this up for a review a while ago but never heard anything. I
just updated it to fit with the current version of the source, and that
affected a change Geoff Blake had made on May 23rd. It would be a good
idea for you ARM folks to look at this and make sure I didn't unfix what
Geoff was fixing with that change.

It's been a while, but I believe this change was necessary for X86_FS on
O3. I have one other old review I'm going to update (support for memory
mapped control registers) and then I'll give it another shot. Maybe the
change I made recently that fixed the store microops dropping faults got
it going? That may just be wishful thinking, but I have to imagine it's
close to working.

Gabe

On 07/03/11 02:44, Gabe Black wrote:
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/501/
> -----------------------------------------------------------
>
> (Updated 2011-07-03 02:44:45.024096)
>
>
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
>
>
> Summary
> -------
>
> O3: Fix corner case squashing into the microcode ROM.
>
> When fetching from the microcode ROM, if the PC is set so that it isn't in the
> cache block that's been fetched the CPU will get stuck. The fetch stage
> notices that it's in the ROM so it doesn't try to fetch from the current PC.
> It then later notices that it's outside of the current cache block so it skips
> generating instructions expecting to continue once the right bytes have been
> fetched. This change lets the fetch stage attempt to generate instructions,
> and only checks if the bytes it's going to use are valid if it's really going
> to use them.
>
>
> Diffs (updated)
> -----
>
>   src/cpu/o3/fetch_impl.hh 1b4b9c05ad2b 
>
> Diff: http://reviews.m5sim.org/r/501/diff
>
>
> Testing
> -------
>
>
> Thanks,
>
> Gabe
>
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