[gem5-dev] changeset in gem5: MOESI_hammer: Fixed uniprocessor DMA bug

[Brad Beckmann]

changeset d59189f372e7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d59189f372e7
description:
        MOESI_hammer: Fixed uniprocessor DMA bug

diffstat:

 src/mem/protocol/MOESI_hammer-cache.sm |  17 ++++++++++++++++-
 src/mem/protocol/MOESI_hammer-dir.sm   |  14 ++++++++++++++
 2 files changed, 30 insertions(+), 1 deletions(-)

diffs (58 lines):

diff -r fad37c6670a6 -r d59189f372e7 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm    Tue Jul 05 18:30:05 2011 -0700
+++ b/src/mem/protocol/MOESI_hammer-cache.sm    Wed Jul 06 18:44:42 2011 -0700
@@ -545,6 +545,21 @@
     }
   }
 
+  action(b_issueGETXIfMoreThanOne, "bo", desc="Issue GETX") {
+    if (machineCount(MachineType:L1Cache) > 1) {
+      enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
+        assert(is_valid(tbe));
+        out_msg.Address := address;
+        out_msg.Type := CoherenceRequestType:GETX;
+        out_msg.Requestor := machineID;
+        out_msg.Destination.add(map_Address_to_Directory(address));
+        out_msg.MessageSize := MessageSizeType:Request_Control;
+        out_msg.InitialRequestTime := get_time();
+      }
+    }
+    tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each 
other cache (n-1) plus the memory (+1)
+  }
+
   action(bf_issueGETF, "bf", desc="Issue GETF") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
       assert(is_valid(tbe));
@@ -921,7 +936,7 @@
 
   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of 
messages for which we're waiting") {
     peek(responseToCache_in, ResponseMsg) {
-      assert(in_msg.Acks > 0);
+      assert(in_msg.Acks >= 0);
       assert(is_valid(tbe));
       DPRINTF(RubySlicc, "Sender = %s\n", in_msg.Sender);
       DPRINTF(RubySlicc, "SilentAcks = %d\n", in_msg.SilentAcks);
diff -r fad37c6670a6 -r d59189f372e7 src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm      Tue Jul 05 18:30:05 2011 -0700
+++ b/src/mem/protocol/MOESI_hammer-dir.sm      Wed Jul 06 18:44:42 2011 -0700
@@ -951,6 +951,20 @@
             }
         }
       }
+    } else {
+      peek(requestQueue_in, RequestMsg) {
+          enqueue(responseNetwork_out, ResponseMsg, latency="1") {
+            out_msg.Address := address;
+            out_msg.Type := CoherenceResponseType:ACK;
+            out_msg.Sender := machineID;
+            out_msg.Destination.add(in_msg.Requestor);
+            out_msg.Dirty := false; // By definition, the block is now clean
+            out_msg.Acks := 0;
+            out_msg.SilentAcks := 0;
+            DPRINTF(RubySlicc, "%d\n", out_msg.Acks);
+            out_msg.MessageSize := MessageSizeType:Response_Control;
+          }
+      }
     }
   }
 
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