> In this case shouldn't the sti instruction cause some form of serialization > in the pipeline and make the cli wait in fetch until it completes? > Otherwise both could go down the pipe and commit together, never allowing > interrupts to happen. But again, I'm not entirely clear how the ISA should > work in respect to this type of instruction.
Is it really necessary for the pipeline to have such a large bubble? In theory an interrupt should just be like a branch that changes the processor mode. I believe that some machines even insert an instruction into the pipeline to do the interrupt. Nate _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
