> On 2011-08-13 08:15:21, Ali Saidi wrote: > > It doesn't change performance does it? > >
Simulated performance no. I didn't explicitly check simulator performance, but I'm sure it's in the noise at most. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/797/#review1456 ----------------------------------------------------------- On 2011-08-13 01:24:07, Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/797/ > ----------------------------------------------------------- > > (Updated 2011-08-13 01:24:07) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: At the end of an instruction, force fetchAddr to something sensible. > > It's possible (though until now very unlikely) for fetchAddr to get out of > sync with the actual PC of the current instruction. This change forcefull > resets fetchAddr at the end of every instruction. > > > Diffs > ----- > > src/cpu/o3/fetch_impl.hh 22a15643e2ca > > Diff: http://reviews.m5sim.org/r/797/diff > > > Testing > ------- > > > Thanks, > > Gabe > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
