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Eh, this is so simple I'll just commit it. - Gabe On 2011-09-05 02:45:20, Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/837/ > ----------------------------------------------------------- > > (Updated 2011-09-05 02:45:20) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > X86,TLB: Make sure the "delayedResponse" variable is always set. > > When an instruction is translated in the x86 TLB, a variable called > delayedResponse is passed back and forth which tracks whether a translation > could be completed immediately, or if there's going to be callback that will > finish things up. If a read was to the internal memory space, memory mapped > registers used to implement things like MSRs, the function hadn't yet gotten > to where delayedResponse was set to false, it's default. That meant that the > value was never set, and the TLB could start waiting for a callback that would > never come. This change simply moves the assignment to above where control > can divert to translateInt(). > > > Diffs > ----- > > src/arch/x86/tlb.cc 09745e0c3dd9 > > Diff: http://reviews.m5sim.org/r/837/diff > > > Testing > ------- > > > Thanks, > > Gabe > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
