changeset b80783571492 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b80783571492
description:
O3: Update stats for new ordering fix.
diffstat:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout |
8 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt |
752 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/simout |
8 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt |
768 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini |
2 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |
8 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt |
690 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini |
2 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/simout |
8 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt |
750 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt |
2098 +++++-----
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout |
10 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt |
1026 ++--
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini |
6 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr |
1 -
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout |
12 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt |
2026 ++++----
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini |
6 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout |
11 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt |
1098 ++--
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini |
6 +-
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout |
10 +-
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt |
1237 ++--
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini |
4 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/simout |
8 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt |
780 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini |
4 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/simout |
8 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt |
722 +-
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini |
4 +-
tests/long/20.parser/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt |
812 +-
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini |
4 +-
tests/long/20.parser/ref/x86/linux/o3-timing/simout |
24 +-
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt |
768 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout |
8 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt |
746 +-
tests/long/30.eon/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/30.eon/ref/arm/linux/o3-timing/simout |
8 +-
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt |
704 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout |
12 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |
680 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt |
768 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout |
8 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt |
742 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/simout |
8 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt |
814 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout |
12 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt |
774 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt |
770 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout |
10 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt |
764 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/simout |
8 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt |
764 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini |
2 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/simout |
10 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt |
722 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini |
3 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout |
8 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt |
518 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini |
3 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout |
6 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt |
240 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini |
3 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/simout |
8 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt |
342 +-
tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini |
3 +-
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout |
4 +-
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt |
8 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini |
2 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/simout |
8 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt |
406 +-
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini |
2 +-
tests/quick/00.hello/ref/mips/linux/simple-atomic/simout |
6 +-
tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt |
10 +-
tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini |
2 +-
tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout |
6 +-
tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt |
10 +-
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini |
2 +-
tests/quick/00.hello/ref/mips/linux/simple-timing/simout |
6 +-
tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt |
10 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini |
3 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/simout |
8 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt |
108 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini |
5 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout |
6 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt |
14 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini |
3 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout |
8 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt |
12 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini |
6 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout |
10 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt |
1092 ++--
109 files changed, 12492 insertions(+), 12504 deletions(-)
diffs (truncated from 31141 to 300 lines):
diff -r a3992291e230 -r b80783571492
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Tue Sep 13
12:58:08 2011 -0400
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Tue Sep 13
12:58:09 2011 -0400
@@ -500,7 +500,7 @@
env=
errout=cerr
euid=100
-executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/gzip
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r a3992291e230 -r b80783571492
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Tue Sep 13
12:58:08 2011 -0400
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Tue Sep 13
12:58:09 2011 -0400
@@ -3,9 +3,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 17 2011 14:47:20
-gem5 started Aug 17 2011 14:50:17
-gem5 executing on nadc-0388
+gem5 compiled Aug 20 2011 16:10:02
+gem5 started Aug 20 2011 16:10:09
+gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d
build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py
build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -41,4 +41,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 145301847500 because target called exit()
+Exiting @ tick 144450185500 because target called exit()
diff -r a3992291e230 -r b80783571492
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Tue Sep 13
12:58:08 2011 -0400
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Tue Sep 13
12:58:09 2011 -0400
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.145302 #
Number of seconds simulated
-sim_ticks 145301847500 #
Number of ticks simulated
+sim_seconds 0.144450 #
Number of seconds simulated
+sim_ticks 144450185500 #
Number of ticks simulated
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 168398 #
Simulator instruction rate (inst/s)
-host_tick_rate 43264868 #
Simulator tick rate (ticks/s)
-host_mem_usage 252140 #
Number of bytes of host memory used
-host_seconds 3358.43 #
Real time elapsed on the host
+host_inst_rate 180758 #
Simulator instruction rate (inst/s)
+host_tick_rate 46168195 #
Simulator tick rate (ticks/s)
+host_mem_usage 205240 #
Number of bytes of host memory used
+host_seconds 3128.78 #
Real time elapsed on the host
sim_insts 565552443 #
Number of instructions simulated
system.cpu.dtb.fetch_hits 0 #
ITB hits
system.cpu.dtb.fetch_misses 0 #
ITB misses
system.cpu.dtb.fetch_acv 0 #
ITB acv
system.cpu.dtb.fetch_accesses 0 #
ITB accesses
-system.cpu.dtb.read_hits 125931819 #
DTB read hits
-system.cpu.dtb.read_misses 26714 #
DTB read misses
+system.cpu.dtb.read_hits 125584378 #
DTB read hits
+system.cpu.dtb.read_misses 26780 #
DTB read misses
system.cpu.dtb.read_acv 0 #
DTB read access violations
-system.cpu.dtb.read_accesses 125958533 #
DTB read accesses
-system.cpu.dtb.write_hits 41424543 #
DTB write hits
-system.cpu.dtb.write_misses 32276 #
DTB write misses
+system.cpu.dtb.read_accesses 125611158 #
DTB read accesses
+system.cpu.dtb.write_hits 41433696 #
DTB write hits
+system.cpu.dtb.write_misses 32002 #
DTB write misses
system.cpu.dtb.write_acv 0 #
DTB write access violations
-system.cpu.dtb.write_accesses 41456819 #
DTB write accesses
-system.cpu.dtb.data_hits 167356362 #
DTB hits
-system.cpu.dtb.data_misses 58990 #
DTB misses
+system.cpu.dtb.write_accesses 41465698 #
DTB write accesses
+system.cpu.dtb.data_hits 167018074 #
DTB hits
+system.cpu.dtb.data_misses 58782 #
DTB misses
system.cpu.dtb.data_acv 0 #
DTB access violations
-system.cpu.dtb.data_accesses 167415352 #
DTB accesses
-system.cpu.itb.fetch_hits 71387266 #
ITB hits
+system.cpu.dtb.data_accesses 167076856 #
DTB accesses
+system.cpu.itb.fetch_hits 70952399 #
ITB hits
system.cpu.itb.fetch_misses 40 #
ITB misses
system.cpu.itb.fetch_acv 0 #
ITB acv
-system.cpu.itb.fetch_accesses 71387306 #
ITB accesses
+system.cpu.itb.fetch_accesses 70952439 #
ITB accesses
system.cpu.itb.read_hits 0 #
DTB read hits
system.cpu.itb.read_misses 0 #
DTB read misses
system.cpu.itb.read_acv 0 #
DTB read access violations
@@ -41,246 +41,246 @@
system.cpu.itb.data_acv 0 #
DTB access violations
system.cpu.itb.data_accesses 0 #
DTB accesses
system.cpu.workload.num_syscalls 17 #
Number of system calls
-system.cpu.numCycles 290603696 #
number of cpu cycles simulated
+system.cpu.numCycles 288900372 #
number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
-system.cpu.BPredUnit.lookups 81919814 #
Number of BP lookups
-system.cpu.BPredUnit.condPredicted 75390266 #
Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 4129357 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 77614173 #
Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 69618230 #
Number of BTB hits
+system.cpu.BPredUnit.lookups 81329377 #
Number of BP lookups
+system.cpu.BPredUnit.condPredicted 74804974 #
Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 4133006 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 77032590 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 69317648 #
Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1955958 #
Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 217 #
Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 74192269 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 739424750 #
Number of instructions fetch has processed
-system.cpu.fetch.Branches 81919814 #
Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 71574188 #
Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 139080989 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 17172234 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 64410456 #
Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 1953991 #
Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 213 #
Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 73654881 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 736311086 #
Number of instructions fetch has processed
+system.cpu.fetch.Branches 81329377 #
Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 71271639 #
Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 138478958 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 16551941 #
Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 64286783 #
Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 31 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 957 #
Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 71387266 #
Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1210642 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 290534603 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.545049 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.198246 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 70952399 #
Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1183706 #
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 288831482 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.549276 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.199825 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 151453614 52.13% 52.13% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 11687885 4.02% 56.15% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 15898742 5.47% 61.62% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 15854935 5.46% 67.08% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 13240035 4.56% 71.64% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 15603650 5.37% 77.01% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 6697784 2.31% 79.31% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3574182 1.23% 80.54% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 56523776 19.46% 100.00% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 150352524 52.06% 52.06% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 11670569 4.04% 56.10% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 15804098 5.47% 61.57% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 15798949 5.47% 67.04% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 13114109 4.54% 71.58% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 15608541 5.40% 76.98% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 6620136 2.29% 79.27% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3484931 1.21% 80.48% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 56377625 19.52% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 290534603 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.281895 #
Number of branch fetches per cycle
-system.cpu.fetch.rate 2.544444 #
Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 90310656 #
Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 50731551 #
Number of cycles decode is blocked
-system.cpu.decode.RunCycles 126219695 #
Number of cycles decode is running
-system.cpu.decode.UnblockCycles 10423604 #
Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 12849097 #
Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4446391 #
Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 868 #
Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 727740839 #
Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3152 #
Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 12849097 #
Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 98621596 #
Number of cycles rename is idle
-system.cpu.rename.BlockCycles 12675857 #
Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 639 #
count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 123066068 #
Number of cycles rename is running
-system.cpu.rename.UnblockCycles 43321346 #
Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 713725381 #
Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 266 #
Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 34127954 #
Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3740820 #
Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 543893835 #
Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 937350842 #
Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 937348775 #
Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2067 #
Number of floating rename lookups
+system.cpu.fetch.rateDist::total 288831482 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.281514 #
Number of branch fetches per cycle
+system.cpu.fetch.rate 2.548668 #
Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 89767727 #
Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 50572891 #
Number of cycles decode is blocked
+system.cpu.decode.RunCycles 125759213 #
Number of cycles decode is running
+system.cpu.decode.UnblockCycles 10322601 #
Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 12409050 #
Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4445174 #
Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 884 #
Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 724769065 #
Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3300 #
Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 12409050 #
Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 98007088 #
Number of cycles rename is idle
+system.cpu.rename.BlockCycles 12678191 #
Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 619 #
count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 122576240 #
Number of cycles rename is running
+system.cpu.rename.UnblockCycles 43160294 #
Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 711155131 #
Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 265 #
Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 33840558 #
Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3866582 #
Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 542435988 #
Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 934956599 #
Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 934954553 #
Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2046 #
Number of floating rename lookups
system.cpu.rename.CommittedMaps 463854889 #
Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 80038946 #
Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 38 #
count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 39 #
count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 85210895 #
count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 131427932 #
Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 43788464 #
Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 14719547 #
Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6869694 #
Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 643138163 #
Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.UndoneMaps 78581099 #
Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 37 #
count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 37 #
count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 84659517 #
count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 130961315 #
Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 43800509 #
Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 14632120 #
Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 10811841 #
Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 641773186 #
Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 30 #
Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 621184561 #
Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 428348 #
Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 76303449 #
Number of squashed instructions iterated over during squash; mainly for
profiling
-system.cpu.iq.iqSquashedOperandsExamined 41228761 #
Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 620620587 #
Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 312645 #
Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 75146534 #
Number of squashed instructions iterated over during squash; mainly for
profiling
+system.cpu.iq.iqSquashedOperandsExamined 39896926 #
Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 13 #
Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 290534603 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.138074 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.876724 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 288831482 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.148729 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.863512 #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
# Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 70371393 24.22% 24.22% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 59001774 20.31% 44.53% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 56407615 19.42% 63.94% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 31734464 10.92% 74.87% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 32252552 11.10% 85.97% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 24569230 8.46% 94.42% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 11680867 4.02% 98.45% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3911059 1.35% 99.79% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 605649 0.21% 100.00% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 69246295 23.97% 23.97% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 56834943 19.68% 43.65% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 56336980 19.51% 63.16% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 34937865 12.10% 75.25% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31450731 10.89% 86.14% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 24967668 8.64% 94.79% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 10438059 3.61% 98.40% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3923057 1.36% 99.76% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 695884 0.24% 100.00% #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 290534603 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 288831482 #
Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4149748 79.41% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 46 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.41% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.41% #
attempts to use FU when none available
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