changeset 33bdc36bf46f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=33bdc36bf46f
description:
Prefetch: Don't prefetch if address is in the write queue.
Check that we're not currently writing back an address the prefetcher
is trying
to prefetch before issuing it. We previously checked the mshrQueue and
the cache
itself, but forgot to check the writeBuffer. This fixes a memory
corrucption
issue with an L2 prefetcher.
diffstat:
src/mem/cache/cache_impl.hh | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diffs (13 lines):
diff -r 5979b029bbb4 -r 33bdc36bf46f src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Tue Sep 13 12:06:13 2011 -0500
+++ b/src/mem/cache/cache_impl.hh Tue Sep 13 12:06:13 2011 -0500
@@ -1437,7 +1437,8 @@
PacketPtr pkt = prefetcher->getPacket();
if (pkt) {
Addr pf_addr = blockAlign(pkt->getAddr());
- if (!tags->findBlock(pf_addr) && !mshrQueue.findMatch(pf_addr)) {
+ if (!tags->findBlock(pf_addr) && !mshrQueue.findMatch(pf_addr) &&
+ !writeBuffer.findMatch(pf_addr)) {
// Update statistic on number of prefetches issued
// (hwpf_mshr_misses)
mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
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