changeset f51e3dce9521 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f51e3dce9521
description:
ARM: update TLB to set request packet ASID field
diffstat:
src/arch/arm/miscregs.hh | 5 +++++
src/arch/arm/tlb.cc | 2 ++
src/arch/arm/tlb.hh | 2 +-
3 files changed, 8 insertions(+), 1 deletions(-)
diffs (39 lines):
diff -r 4e09d02322fb -r f51e3dce9521 src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Tue Sep 13 12:06:13 2011 -0500
+++ b/src/arch/arm/miscregs.hh Tue Sep 13 12:06:13 2011 -0500
@@ -436,6 +436,11 @@
Bitfield<31,30> or7;
EndBitUnion(NMRR)
+ BitUnion32(CONTEXTIDR)
+ Bitfield<7,0> asid;
+ Bitfield<31,8> procid;
+ EndBitUnion(CONTEXTIDR)
+
BitUnion32(L2CTLR)
Bitfield<2,0> sataRAMLatency;
Bitfield<4,3> reserved_4_3;
diff -r 4e09d02322fb -r f51e3dce9521 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Tue Sep 13 12:06:13 2011 -0500
+++ b/src/arch/arm/tlb.cc Tue Sep 13 12:06:13 2011 -0500
@@ -467,6 +467,8 @@
bool is_write = (mode == Write);
bool is_priv = isPriv && !(flags & UserMode);
+ req->setAsid(contextId.asid);
+
DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
isPriv, flags & UserMode);
// If this is a clrex instruction, provide a PA of 0 with no fault
diff -r 4e09d02322fb -r f51e3dce9521 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Tue Sep 13 12:06:13 2011 -0500
+++ b/src/arch/arm/tlb.hh Tue Sep 13 12:06:13 2011 -0500
@@ -222,7 +222,7 @@
protected:
SCTLR sctlr;
bool isPriv;
- uint32_t contextId;
+ CONTEXTIDR contextId;
PRRR prrr;
NMRR nmrr;
uint32_t dacr;
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