Thanks for the clarification. I'm currently tracking a bug that is violating the semantics of the IsDelayedCommit flag but am still in the process of determining how exactly.
Geoff On Mon, Nov 28, 2011 at 3:10 PM, Gabe Black <[email protected]> wrote: > IsDelayedCommit may not be named very well. The original intention was > that the CPU would wait until it saw an instruction complete with that > not set, and then set everything that was ready to commit up to that > point. That was impractical, so what it does now is tell the CPU that > there is not a commit point after this instruction so interrupts should > not be recognized there, and it should wait until after an instruction > where that isn't set. > > If I remember correctly the VFP instructions are a little unusual in > that they can be macroops, microops, or normal instructions all on their > own. If they're microops, all but the last should have IsDelayedCommit > set so that the instruction isn't interrupted partway through. If it's a > macroop that flag doesn't matter since it's not actually executed. If > it's a regular instruction it shouldn't be set at all. > > A while ago I sent an email about how register numbering is handled, and > it ended up in the wiki here: > http://www.gem5.org/Architectural_State > Let me know if you need more explanation than that. > > The register constants are defined in arch/arm/intregs.hh. Most of them > are just the integer registers in each bank, aliased appropriately, and > there are a few extras which are fairly obviously named. > > Gabe > > On 11/28/11 10:08, Geoffrey Blake wrote: >> Hey all, >> >> For macroinstructions, what exactly does the IsDelayedCommit supposed >> to mean and force the O3 cpu to do? I have a basic understanding that >> it means the macroinstruction can't be interrupted, but not sure if >> that is actually the correct interpretation. Can someone please >> clarify? >> >> Also, when looking at some traces of the O3 cpu I see registers like >> r34, r35 etc. Where can I find the definition of these registers in >> M5 and the purpose of them in the ARMv7 ISA docs? >> >> Thanks, >> Geoff >> _______________________________________________ >> gem5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/gem5-dev > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
