changeset b1838faf3bcc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b1838faf3bcc
description:
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
diffstat:
configs/common/FSConfig.py | 12 +-
configs/example/se.py | 14 ++
configs/ruby/Ruby.py | 24 +++
src/arch/alpha/freebsd/system.cc | 8 +-
src/arch/alpha/linux/process.cc | 6 +-
src/arch/alpha/linux/system.cc | 26 ++-
src/arch/alpha/linux/system.hh | 5 +
src/arch/alpha/linux/threadinfo.hh | 2 +-
src/arch/alpha/remote_gdb.cc | 2 +-
src/arch/alpha/stacktrace.cc | 12 +-
src/arch/alpha/system.cc | 50 ++++---
src/arch/alpha/system.hh | 6 +
src/arch/alpha/tru64/process.cc | 18 +-
src/arch/alpha/tru64/system.cc | 6 +-
src/arch/alpha/utility.cc | 4 +-
src/arch/alpha/vtophys.cc | 6 +-
src/arch/alpha/vtophys.hh | 4 +-
src/arch/arm/linux/process.cc | 12 +-
src/arch/arm/linux/system.cc | 40 +++--
src/arch/arm/process.cc | 1 -
src/arch/arm/stacktrace.cc | 6 +-
src/arch/arm/system.cc | 34 ++--
src/arch/arm/system.hh | 5 +-
src/arch/arm/utility.cc | 4 +-
src/arch/arm/vtophys.cc | 4 +-
src/arch/mips/linux/process.cc | 6 +-
src/arch/mips/linux/system.cc | 4 +-
src/arch/mips/linux/threadinfo.hh | 2 +-
src/arch/mips/stacktrace.cc | 8 +-
src/arch/mips/utility.cc | 4 +-
src/arch/power/linux/process.cc | 2 +-
src/arch/power/process.cc | 1 -
src/arch/sparc/linux/syscalls.cc | 8 +-
src/arch/sparc/process.cc | 5 +-
src/arch/sparc/solaris/process.cc | 2 +-
src/arch/sparc/system.cc | 39 +---
src/arch/sparc/system.hh | 14 +-
src/arch/sparc/utility.cc | 4 +-
src/arch/sparc/vtophys.cc | 4 +-
src/arch/x86/bios/intelmp.cc | 156 +++++++++++-----------
src/arch/x86/bios/intelmp.hh | 24 +-
src/arch/x86/bios/smbios.cc | 78 +++++-----
src/arch/x86/bios/smbios.hh | 10 +-
src/arch/x86/linux/syscalls.cc | 12 +-
src/arch/x86/linux/system.cc | 12 +-
src/arch/x86/process.cc | 1 -
src/arch/x86/stacktrace.cc | 14 +-
src/arch/x86/system.cc | 43 +++---
src/base/loader/elf_object.cc | 6 +-
src/base/loader/elf_object.hh | 2 +-
src/base/loader/hex_file.cc | 6 +-
src/base/loader/hex_file.hh | 4 +-
src/base/loader/object_file.cc | 16 +-
src/base/loader/object_file.hh | 6 +-
src/base/remote_gdb.cc | 12 +-
src/cpu/checker/thread_context.hh | 8 +-
src/cpu/inorder/cpu.cc | 13 +-
src/cpu/inorder/cpu.hh | 4 -
src/cpu/inorder/resources/cache_unit.cc | 15 --
src/cpu/inorder/resources/cache_unit.hh | 2 -
src/cpu/inorder/thread_context.cc | 6 +-
src/cpu/inorder/thread_context.hh | 10 +-
src/cpu/o3/cpu.cc | 12 +-
src/cpu/o3/cpu.hh | 4 -
src/cpu/o3/lsq.hh | 7 -
src/cpu/o3/lsq_impl.hh | 13 -
src/cpu/o3/thread_context.hh | 10 +-
src/cpu/o3/thread_context_impl.hh | 6 +-
src/cpu/ozone/cpu.hh | 8 +-
src/cpu/ozone/cpu_impl.hh | 18 +--
src/cpu/simple/atomic.cc | 15 +-
src/cpu/simple/atomic.hh | 11 +-
src/cpu/simple/timing.cc | 15 +-
src/cpu/simple/timing.hh | 2 -
src/cpu/simple_thread.cc | 8 +-
src/cpu/simple_thread.hh | 4 +-
src/cpu/thread_context.hh | 28 ++-
src/cpu/thread_state.cc | 102 +++++----------
src/cpu/thread_state.hh | 42 ++---
src/dev/simple_disk.cc | 4 +-
src/kern/tru64/tru64.hh | 63 ++++----
src/kern/tru64/tru64_events.cc | 4 +-
src/mem/SConscript | 4 +-
src/mem/fs_translating_port_proxy.cc | 162 ++++++++++++++++++++++++
src/mem/fs_translating_port_proxy.hh | 104 +++++++++++++++
src/mem/port.hh | 44 ------
src/mem/port_impl.hh | 53 --------
src/mem/port_proxy.hh | 174 ++++++++++++++++++++++++++
src/mem/ruby/system/RubyPort.cc | 7 +-
src/mem/ruby/system/RubyPortProxy.cc | 70 ++++++++++
src/mem/ruby/system/RubyPortProxy.hh | 114 +++++++++++++++++
src/mem/ruby/system/SConscript | 1 +
src/mem/ruby/system/Sequencer.py | 3 +
src/mem/se_translating_port_proxy.cc | 211 ++++++++++++++++++++++++++++++++
src/mem/se_translating_port_proxy.hh | 99 +++++++++++++++
src/mem/translating_port.cc | 199 ------------------------------
src/mem/translating_port.hh | 73 -----------
src/mem/vport.cc | 117 -----------------
src/mem/vport.hh | 85 ------------
src/sim/arguments.hh | 2 +-
src/sim/process.cc | 10 +-
src/sim/process.hh | 4 +-
src/sim/process_impl.hh | 10 +-
src/sim/syscall_emul.cc | 30 ++--
src/sim/syscall_emul.hh | 62 ++++----
src/sim/system.cc | 124 +++++++++---------
src/sim/system.hh | 14 +-
src/sim/vptr.hh | 6 +-
tests/configs/inorder-timing.py | 1 +
tests/configs/memtest-ruby.py | 4 +
tests/configs/memtest.py | 2 +
tests/configs/o3-timing-mp.py | 2 +
tests/configs/o3-timing.py | 1 +
tests/configs/rubytest-ruby.py | 3 +
tests/configs/simple-atomic-mp.py | 2 +
tests/configs/simple-atomic.py | 1 +
tests/configs/simple-timing-mp-ruby.py | 3 +
tests/configs/simple-timing-mp.py | 2 +
tests/configs/simple-timing-ruby.py | 3 +
tests/configs/simple-timing.py | 1 +
120 files changed, 1689 insertions(+), 1368 deletions(-)
diffs (truncated from 6059 to 300 lines):
diff -r ab0d7b7d9989 -r b1838faf3bcc configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Tue Jan 17 12:55:07 2012 -0600
+++ b/configs/common/FSConfig.py Tue Jan 17 12:55:08 2012 -0600
@@ -1,4 +1,4 @@
-# Copyright (c) 2010 ARM Limited
+# Copyright (c) 2010-2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -91,6 +91,8 @@
self.console = binary('console')
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+ self.system_port = self.membus.port
+
return self
def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
@@ -183,6 +185,8 @@
self.hypervisor_desc_bin = binary('1up-hv.bin')
self.partition_desc_bin = binary('1up-md.bin')
+ self.system_port = self.membus.port
+
return self
def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
@@ -263,6 +267,8 @@
self.terminal = Terminal()
self.vncserver = VncServer()
+ self.system_port = self.membus.port
+
return self
@@ -301,6 +307,8 @@
self.console = binary('mips/console')
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+ self.system_port = self.membus.port
+
return self
def x86IOAddress(port):
@@ -320,6 +328,8 @@
# connect the io bus
x86_sys.pc.attachIO(x86_sys.iobus)
+ x86_sys.system_port = x86_sys.membus.port
+
def connectX86RubySystem(x86_sys):
# North Bridge
x86_sys.piobus = Bus(bus_id=0)
diff -r ab0d7b7d9989 -r b1838faf3bcc configs/example/se.py
--- a/configs/example/se.py Tue Jan 17 12:55:07 2012 -0600
+++ b/configs/example/se.py Tue Jan 17 12:55:08 2012 -0600
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
@@ -179,7 +191,9 @@
options.use_map = True
Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+ system.system_port = system.ruby._sys_port_proxy.port
else:
+ system.system_port = system.membus.port
system.physmem.port = system.membus.port
CacheConfig.config_cache(options, system)
diff -r ab0d7b7d9989 -r b1838faf3bcc configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py Tue Jan 17 12:55:07 2012 -0600
+++ b/configs/ruby/Ruby.py Tue Jan 17 12:55:08 2012 -0600
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# Copyright (c) 2009 Advanced Micro Devices, Inc.
# All rights reserved.
@@ -82,6 +94,17 @@
print "Error: could not create sytem for ruby protocol %s" % protocol
raise
+ # Create a port proxy for connecting the system port. This is
+ # independent of the protocol and kept in the protocol-agnostic
+ # part (i.e. here).
+ sys_port_proxy = RubyPortProxy(version = 0,
+ physMemPort = system.physmem.port,
+ physmem = system.physmem,
+ ruby_system = ruby)
+ # Give the system port proxy a SimObject parent without creating a
+ # full-fledged controller
+ system.sys_port_proxy = sys_port_proxy
+
#
# Set the network classes based on the command line options
#
@@ -159,4 +182,5 @@
ruby.profiler = ruby_profiler
ruby.mem_size = total_mem_size
ruby._cpu_ruby_ports = cpu_sequencers
+ ruby._sys_port_proxy = sys_port_proxy
ruby.random_seed = options.random_seed
diff -r ab0d7b7d9989 -r b1838faf3bcc src/arch/alpha/freebsd/system.cc
--- a/src/arch/alpha/freebsd/system.cc Tue Jan 17 12:55:07 2012 -0600
+++ b/src/arch/alpha/freebsd/system.cc Tue Jan 17 12:55:08 2012 -0600
@@ -41,9 +41,7 @@
#include "arch/vtophys.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
-#include "mem/physical.hh"
-#include "mem/port.hh"
-#include "mem/vport.hh"
+#include "mem/fs_translating_port_proxy.hh"
#include "sim/byteswap.hh"
#define TIMER_FREQUENCY 1193180
@@ -78,8 +76,8 @@
ppc_vaddr = (Addr)tc->readIntReg(17);
timer_vaddr = (Addr)tc->readIntReg(18);
- virtPort->write(ppc_vaddr, (uint32_t)SimClock::Frequency);
- virtPort->write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
+ virtProxy->write(ppc_vaddr, (uint32_t)SimClock::Frequency);
+ virtProxy->write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
}
void
diff -r ab0d7b7d9989 -r b1838faf3bcc src/arch/alpha/linux/process.cc
--- a/src/arch/alpha/linux/process.cc Tue Jan 17 12:55:07 2012 -0600
+++ b/src/arch/alpha/linux/process.cc Tue Jan 17 12:55:08 2012 -0600
@@ -56,7 +56,7 @@
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "alpha");
- name.copyOut(tc->getMemPort());
+ name.copyOut(tc->getMemProxy());
return 0;
}
@@ -78,7 +78,7 @@
TypedBufferArg<uint64_t> fpcr(bufPtr);
// I don't think this exactly matches the HW FPCR
*fpcr = 0;
- fpcr.copyOut(tc->getMemPort());
+ fpcr.copyOut(tc->getMemProxy());
return 0;
}
@@ -106,7 +106,7 @@
case 14: { // SSI_IEEE_FP_CONTROL
TypedBufferArg<uint64_t> fpcr(bufPtr);
// I don't think this exactly matches the HW FPCR
- fpcr.copyIn(tc->getMemPort());
+ fpcr.copyIn(tc->getMemProxy());
DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
" setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
return 0;
diff -r ab0d7b7d9989 -r b1838faf3bcc src/arch/alpha/linux/system.cc
--- a/src/arch/alpha/linux/system.cc Tue Jan 17 12:55:07 2012 -0600
+++ b/src/arch/alpha/linux/system.cc Tue Jan 17 12:55:08 2012 -0600
@@ -64,6 +64,17 @@
LinuxAlphaSystem::LinuxAlphaSystem(Params *p)
: AlphaSystem(p)
{
+}
+
+void
+LinuxAlphaSystem::initState()
+{
+ // Moved from the constructor to here since it relies on the
+ // address map being resolved in the interconnect
+
+ // Call the initialisation of the super class
+ AlphaSystem::initState();
+
Addr addr = 0;
/**
@@ -78,8 +89,9 @@
* Since we aren't using a bootloader, we have to copy the
* kernel arguments directly into the kernel's memory.
*/
- virtPort->writeBlob(CommandLine(),
(uint8_t*)params()->boot_osflags.c_str(),
- params()->boot_osflags.length()+1);
+ virtProxy->writeBlob(CommandLine(),
+ (uint8_t*)params()->boot_osflags.c_str(),
+ params()->boot_osflags.length()+1);
/**
* find the address of the est_cycle_freq variable and insert it
@@ -87,8 +99,8 @@
* calculated it by using the PIT, RTC, etc.
*/
if (kernelSymtab->findAddress("est_cycle_freq", addr))
- virtPort->write(addr, (uint64_t)(SimClock::Frequency /
- p->boot_cpu_frequency));
+ virtProxy->write(addr, (uint64_t)(SimClock::Frequency /
+ params()->boot_cpu_frequency));
/**
@@ -98,7 +110,7 @@
* 255 ASNs.
*/
if (kernelSymtab->findAddress("dp264_mv", addr))
- virtPort->write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
+ virtProxy->write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
else
panic("could not find dp264_mv\n");
@@ -165,9 +177,9 @@
if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
Tick cpuFreq = tc->getCpuPtr()->frequency();
Tick intrFreq = platform->intrFrequency();
- VirtualPort *vp;
+ FSTranslatingPortProxy* vp;
- vp = tc->getVirtPort();
+ vp = tc->getVirtProxy();
vp->writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988));
}
}
diff -r ab0d7b7d9989 -r b1838faf3bcc src/arch/alpha/linux/system.hh
--- a/src/arch/alpha/linux/system.hh Tue Jan 17 12:55:07 2012 -0600
+++ b/src/arch/alpha/linux/system.hh Tue Jan 17 12:55:08 2012 -0600
@@ -128,6 +128,11 @@
LinuxAlphaSystem(Params *p);
~LinuxAlphaSystem();
+ /**
+ * Initialise the system
+ */
+ virtual void initState();
+
void setDelayLoop(ThreadContext *tc);
};
diff -r ab0d7b7d9989 -r b1838faf3bcc src/arch/alpha/linux/threadinfo.hh
--- a/src/arch/alpha/linux/threadinfo.hh Tue Jan 17 12:55:07 2012 -0600
+++ b/src/arch/alpha/linux/threadinfo.hh Tue Jan 17 12:55:08 2012 -0600
@@ -78,7 +78,7 @@
if (!addr)
addr = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23);
- FunctionalPort *p = tc->getPhysPort();
+ PortProxy* p = tc->getPhysProxy();
p->readBlob(addr, (uint8_t *)&sp, sizeof(Addr));
return sp & ~ULL(0x3fff);
diff -r ab0d7b7d9989 -r b1838faf3bcc src/arch/alpha/remote_gdb.cc
--- a/src/arch/alpha/remote_gdb.cc Tue Jan 17 12:55:07 2012 -0600
+++ b/src/arch/alpha/remote_gdb.cc Tue Jan 17 12:55:08 2012 -0600
@@ -192,7 +192,7 @@
Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20);
PageTableEntry pte =
- kernel_pte_lookup(context->getPhysPort(), ptbr, va);
+ kernel_pte_lookup(context->getPhysProxy(), ptbr, va);
if (!pte.valid()) {
DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
return false;
diff -r ab0d7b7d9989 -r b1838faf3bcc src/arch/alpha/stacktrace.cc
--- a/src/arch/alpha/stacktrace.cc Tue Jan 17 12:55:07 2012 -0600
+++ b/src/arch/alpha/stacktrace.cc Tue Jan 17 12:55:08 2012 -0600
@@ -37,7 +37,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "mem/vport.hh"
+#include "mem/fs_translating_port_proxy.hh"
#include "sim/system.hh"
using namespace std;
@@ -48,7 +48,7 @@
: tc(_tc)
{
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