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Ship it! - Ali On 2012-01-18 02:34:02, Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/1003/ > ----------------------------------------------------------- > > (Updated 2012-01-18 02:34:02) > > > Review request for Default. > > > Summary > ------- > > MEM: Remove the otherPort from the cache ports > > This patch is a very straight-forward simplification, removing the > unecessary otherPort pointer from the cache port. The pointer was only > used to forward range changes, and the address range is fixed for the > cache. Removing the pointer simplifies the transition to master/slave > ports. > > > Diffs > ----- > > src/mem/cache/base.hh 03e09db82c80 > src/mem/cache/base.cc 03e09db82c80 > src/mem/cache/cache_impl.hh 03e09db82c80 > > Diff: http://reviews.m5sim.org/r/1003/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
