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Ship it! When I use this patch with the O3 CPU and Ruby combination, things work as they should. - Nilay Vaish On Jan. 18, 2012, 2:35 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1005/ > ----------------------------------------------------------- > > (Updated Jan. 18, 2012, 2:35 a.m.) > > > Review request for Default. > > > Description > ------- > > MEM: Make the RubyPort physMemPort a PioPort instead of M5Port > > This patch makes the physMemPort of the RubyPort a PioPort rather than > an M5Port. This reflects the fact that the M5Port and PioPort have > different roles. The M5Port is really a coherent slave that is > connected to the CPUs and other coherent masters of the system, > e.g. DMA ports. The PioPort, on the other hand, is a master port that > is connected to the memory and other slaves, for example the pio > devices. > > This simplifies future changes into master/slave ports and is > consistent with the port roles throughout the system. > > > Diffs > ----- > > src/mem/ruby/system/RubyPort.hh 03e09db82c80 > src/mem/ruby/system/RubyPort.cc 03e09db82c80 > > Diff: http://reviews.gem5.org/r/1005/diff/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
