> On Feb. 9, 2012, 2:03 a.m., Gabe Black wrote: > > src/cpu/o3/iew_impl.hh, line 1620 > > <http://reviews.gem5.org/r/1032/diff/1/?file=23072#file23072line1620> > > > > This looks pretty strange. Was this dead code? Did you bring it back to > > life here on purpose? Or in other words, is reintroducing it the right > > thing to do, or is it obsolete code? > > Geoffrey Blake wrote: > It was guarded by a #ifdef TARGET_ALPHA which has somewhere along the way > ceased to exist. Not sure if it's dead code or not. If it is I'll just > remove it. > > Gabe Black wrote: > I'm not sure either. Please take a look and see what you think. I'll > leave it up to you.
After digging some in the source this looks like code that should be included. The ARM, x86 and ALPHA ISAs all have software prefetch instructions (IsDataPrefetch instruction flag in the ISA definitions) that this piece of code would count instead of lumping them with all the instructions. There is another code snippet like this in src/cpu/o3/commit_impl.hh as well. I guess Steve, Nate or Ali can offer their opinions on whether this stat is wanted or needed. - Geoffrey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1032/#review2099 ----------------------------------------------------------- On Feb. 10, 2012, 3:25 p.m., Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1032/ > ----------------------------------------------------------- > > (Updated Feb. 10, 2012, 3:25 p.m.) > > > Review request for Default. > > > Description > ------- > > CheckerCPU: Add function stubs to non-ARM ISA source to compile with > CheckerCPU > > Making the CheckerCPU a runtime time option requires the code to be compatible > with ISAs other than ARM. This patch adds the appropriate function > stubs to allow compilation. > > > Diffs > ----- > > src/arch/alpha/tlb.hh 8f354c5a1634 > src/arch/alpha/tlb.cc 8f354c5a1634 > src/arch/mips/tlb.hh 8f354c5a1634 > src/arch/mips/tlb.cc 8f354c5a1634 > src/arch/power/tlb.hh 8f354c5a1634 > src/arch/power/tlb.cc 8f354c5a1634 > src/arch/sparc/tlb.hh 8f354c5a1634 > src/arch/sparc/tlb.cc 8f354c5a1634 > src/arch/x86/tlb.hh 8f354c5a1634 > src/arch/x86/tlb.cc 8f354c5a1634 > src/cpu/checker/cpu.hh 8f354c5a1634 > src/cpu/checker/cpu_impl.hh 8f354c5a1634 > src/cpu/inorder/thread_context.hh 8f354c5a1634 > src/cpu/o3/commit_impl.hh 8f354c5a1634 > src/cpu/o3/iew_impl.hh 8f354c5a1634 > src/cpu/ozone/back_end_impl.hh 8f354c5a1634 > src/cpu/ozone/lw_back_end_impl.hh 8f354c5a1634 > > Diff: http://reviews.gem5.org/r/1032/diff/diff > > > Testing > ------- > > Compiles for all ISAs. > > > Thanks, > > Geoffrey Blake > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
