changeset 7e966326ef5b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7e966326ef5b
description:
MEM: Move port creation to the memory object(s) construction
This patch moves all port creation from the getPort method to be
consistently done in the MemObject's constructor. This is possible
thanks to the Swig interface passing the length of the vector ports.
Previously there was a mix of: 1) creating the ports as members (at
object construction time) and using getPort for the name resolution,
or 2) dynamically creating the ports in the getPort call. This is now
uniform. Furthermore, objects that would not be complete without a
port have these ports as members rather than having pointers to
dynamically allocated ports.
This patch also enables an elaboration-time enumeration of all the
ports in the system which can be used to determine the masterId.
diffstat:
src/arch/arm/table_walker.cc | 33 +++++-------
src/arch/arm/table_walker.hh | 3 +-
src/arch/x86/interrupts.cc | 5 +-
src/arch/x86/interrupts.hh | 8 ++-
src/cpu/testers/directedtest/RubyDirectedTester.cc | 34 +++++++++----
src/cpu/testers/rubytest/RubyTester.cc | 33 ++++++++----
src/dev/alpha/tsunami_pchip.cc | 3 +-
src/dev/arm/pl111.cc | 6 +-
src/dev/copy_engine.cc | 42 ++++++++--------
src/dev/copy_engine.hh | 2 +-
src/dev/i8254xGBe.cc | 2 +-
src/dev/io_device.cc | 39 +++++++--------
src/dev/io_device.hh | 20 ++++---
src/dev/mips/malta_pchip.cc | 3 +-
src/dev/pcidev.cc | 16 +++--
src/dev/pcidev.hh | 9 +--
src/dev/sinic.cc | 2 +-
src/dev/x86/i82094aa.cc | 4 +-
src/dev/x86/i82094aa.hh | 2 +-
src/dev/x86/intdev.cc | 4 +-
src/dev/x86/intdev.hh | 11 +---
src/mem/bridge.cc | 40 +++++++--------
src/mem/bridge.hh | 22 ++++----
src/mem/bus.cc | 55 ++++++++++++++++-----
src/mem/bus.hh | 5 ++
src/mem/physical.cc | 27 ++++------
src/mem/ruby/system/RubyPort.cc | 39 +++++----------
src/mem/ruby/system/RubyPort.hh | 4 +-
28 files changed, 253 insertions(+), 220 deletions(-)
diffs (truncated from 1252 to 300 lines):
diff -r ed91b534ed04 -r 7e966326ef5b src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Fri Feb 24 11:42:00 2012 -0500
+++ b/src/arch/arm/table_walker.cc Fri Feb 24 11:43:53 2012 -0500
@@ -45,13 +45,14 @@
#include "debug/Checkpoint.hh"
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
-#include "dev/io_device.hh"
#include "sim/system.hh"
using namespace ArmISA;
TableWalker::TableWalker(const Params *p)
- : MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false),
+ : MemObject(p), port(this, params()->sys, params()->min_backoff,
+ params()->max_backoff, true),
+ tlb(NULL), currState(NULL), pending(false),
masterId(p->sys->getMasterId(name())),
doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
{
@@ -94,13 +95,7 @@
TableWalker::getPort(const std::string &if_name, int idx)
{
if (if_name == "port") {
- if (port != NULL)
- return port;
- System *sys = params()->sys;
- Tick minb = params()->min_backoff;
- Tick maxb = params()->max_backoff;
- port = new DmaPort(this, sys, minb, maxb, true);
- return port;
+ return &port;
}
return NULL;
}
@@ -225,24 +220,24 @@
}
if (currState->timing) {
- port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
- &doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
- currState->tc->getCpuPtr()->ticks(1), flag);
+ port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
+ &doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
+ currState->tc->getCpuPtr()->ticks(1), flag);
DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding:
%d\n",
stateQueueL1.size());
stateQueueL1.push_back(currState);
currState = NULL;
} else if (!currState->functional) {
- port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
- NULL, (uint8_t*)&currState->l1Desc.data,
- currState->tc->getCpuPtr()->ticks(1), flag);
+ port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
+ NULL, (uint8_t*)&currState->l1Desc.data,
+ currState->tc->getCpuPtr()->ticks(1), flag);
doL1Descriptor();
f = currState->fault;
} else {
RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag,
masterId);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
- port->sendFunctional(pkt);
+ port.sendFunctional(pkt);
doL1Descriptor();
delete req;
delete pkt;
@@ -574,11 +569,11 @@
if (currState->timing) {
currState->delayed = true;
- port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
+ port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
&doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
currState->tc->getCpuPtr()->ticks(1));
} else if (!currState->functional) {
- port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
+ port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
NULL, (uint8_t*)&currState->l2Desc.data,
currState->tc->getCpuPtr()->ticks(1));
doL2Descriptor();
@@ -586,7 +581,7 @@
RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0,
masterId);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq,
Packet::Broadcast);
pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
- port->sendFunctional(pkt);
+ port.sendFunctional(pkt);
doL2Descriptor();
delete req;
delete pkt;
diff -r ed91b534ed04 -r 7e966326ef5b src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh Fri Feb 24 11:42:00 2012 -0500
+++ b/src/arch/arm/table_walker.hh Fri Feb 24 11:43:53 2012 -0500
@@ -44,6 +44,7 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/tlb.hh"
+#include "dev/io_device.hh"
#include "mem/mem_object.hh"
#include "mem/request.hh"
#include "params/ArmTableWalker.hh"
@@ -328,7 +329,7 @@
/** Port to issue translation requests from */
- DmaPort *port;
+ DmaPort port;
/** TLB that is initiating these table walks */
TLB *tlb;
diff -r ed91b534ed04 -r 7e966326ef5b src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc Fri Feb 24 11:42:00 2012 -0500
+++ b/src/arch/x86/interrupts.cc Fri Feb 24 11:43:53 2012 -0500
@@ -554,7 +554,7 @@
break;
}
pendingIPIs += apics.size();
- intPort->sendMessage(apics, message, timing);
+ intPort.sendMessage(apics, message, timing);
newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
}
break;
@@ -612,7 +612,8 @@
pendingInit(false), initVector(0),
pendingStartup(false), startupVector(0),
startedUp(false), pendingUnmaskableInt(false),
- pendingIPIs(0), cpu(NULL)
+ pendingIPIs(0), cpu(NULL),
+ intSlavePort(name() + ".int_slave", this, this, latency)
{
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));
diff -r ed91b534ed04 -r 7e966326ef5b src/arch/x86/interrupts.hh
--- a/src/arch/x86/interrupts.hh Fri Feb 24 11:42:00 2012 -0500
+++ b/src/arch/x86/interrupts.hh Fri Feb 24 11:43:53 2012 -0500
@@ -188,6 +188,9 @@
int initialApicId;
+ // Port for receiving interrupts
+ IntPort intSlavePort;
+
public:
int getInitialApicId() { return initialApicId; }
@@ -242,10 +245,9 @@
// Python class we also need two ports even if they are
// identical
if (if_name == "int_master") {
- return intPort;
+ return &intPort;
} else if (if_name == "int_slave") {
- // memory leak...but will be removed in the next patch
- return new IntPort(name() + ".int_slave", this, this, latency);
+ return &intSlavePort;
}
return BasicPioDevice::getPort(if_name, idx);
}
diff -r ed91b534ed04 -r 7e966326ef5b
src/cpu/testers/directedtest/RubyDirectedTester.cc
--- a/src/cpu/testers/directedtest/RubyDirectedTester.cc Fri Feb 24
11:42:00 2012 -0500
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc Fri Feb 24
11:43:53 2012 -0500
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -40,6 +52,12 @@
{
m_requests_completed = 0;
+ // create the ports
+ for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
+ ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
+ this, i));
+ }
+
// add the check start event to the event queue
schedule(directedStartEvent, 1);
}
@@ -61,21 +79,15 @@
RubyDirectedTester::getPort(const std::string &if_name, int idx)
{
if (if_name != "cpuPort") {
- panic("RubyDirectedTester::getPort: unknown port %s requested",
if_name);
+ panic("RubyDirectedTester::getPort: unknown port %s requested",
+ if_name);
}
- if (idx >= (int)ports.size()) {
- ports.resize(idx + 1);
+ if (idx >= static_cast<int>(ports.size())) {
+ panic("RubyDirectedTester::getPort: unknown index %d requested\n",
idx);
}
- if (ports[idx] != NULL) {
- panic("RubyDirectedTester::getPort: port %d already assigned", idx);
- }
-
- CpuPort *port = new CpuPort(csprintf("%s-port%d", name(), idx), this, idx);
-
- ports[idx] = port;
- return port;
+ return ports[idx];
}
Tick
diff -r ed91b534ed04 -r 7e966326ef5b src/cpu/testers/rubytest/RubyTester.cc
--- a/src/cpu/testers/rubytest/RubyTester.cc Fri Feb 24 11:42:00 2012 -0500
+++ b/src/cpu/testers/rubytest/RubyTester.cc Fri Feb 24 11:43:53 2012 -0500
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* Copyright (c) 2009 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -48,6 +60,12 @@
{
m_checks_completed = 0;
+ // create the ports
+ for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
+ ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
+ this, i));
+ }
+
// add the check start event to the event queue
schedule(checkStartEvent, 1);
}
@@ -78,21 +96,14 @@
RubyTester::getPort(const std::string &if_name, int idx)
{
if (if_name != "cpuPort") {
- panic("RubyTester::getPort: unknown port %s requested", if_name);
+ panic("RubyTester::getPort: unknown port %s requested\n", if_name);
}
- if (idx >= (int)ports.size()) {
- ports.resize(idx + 1);
+ if (idx >= static_cast<int>(ports.size())) {
+ panic("RubyTester::getPort: unknown index %d requested\n", idx);
}
- if (ports[idx] != NULL) {
- panic("RubyTester::getPort: port %d already assigned", idx);
- }
-
- CpuPort *port = new CpuPort(csprintf("%s-port%d", name(), idx), this, idx);
-
- ports[idx] = port;
- return port;
+ return ports[idx];
}
Tick
diff -r ed91b534ed04 -r 7e966326ef5b src/dev/alpha/tsunami_pchip.cc
--- a/src/dev/alpha/tsunami_pchip.cc Fri Feb 24 11:42:00 2012 -0500
+++ b/src/dev/alpha/tsunami_pchip.cc Fri Feb 24 11:43:53 2012 -0500
@@ -284,7 +284,8 @@
baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
- pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry,
sizeof(uint64_t));
+ pioPort.readBlob(pteAddr, (uint8_t*)&pteEntry,
+ sizeof(uint64_t));
dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr &
ULL(0x1fff));
diff -r ed91b534ed04 -r 7e966326ef5b src/dev/arm/pl111.cc
--- a/src/dev/arm/pl111.cc Fri Feb 24 11:42:00 2012 -0500
+++ b/src/dev/arm/pl111.cc Fri Feb 24 11:43:53 2012 -0500
@@ -460,9 +460,9 @@
// will be uncacheable as well. If we have uncacheable and cacheable
// requests in the memory system for the same address it won't be
// pleased
- dmaPort->dmaAction(MemCmd::ReadReq, curAddr + startAddr, dmaSize,
- &dmaDoneEvent[dmaPendingNum-1], curAddr + dmaBuffer, 0,
- Request::UNCACHEABLE);
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