> On Feb. 29, 2012, 2:39 a.m., Andreas Hansson wrote: > > I'd like to see a check in cpu/base.cc to ensure that the interrupts are > > really set properly. Currently it seems that failing to call > > createInterrupts would result in a segfault. > > Nilay Vaish wrote: > There is a check on line 224. I can add assert in the takeOver function. > > Andreas Hansson wrote: > I was thinking: if not deferred, make sure interrupt is not NULL. > > Nilay Vaish wrote: > Would deferred registration be set to true for the checker CPU? I doubt > that. > > Andreas Hansson wrote: > No no, I'm just saying, for a CPU that is not switched in later, i.e. up > and running from time 0, make sure it actually has an interrupt controller > (that someone called createInterrupts).
I think it is not possible to put in such a check. Again, the checker CPU, even though would be running right from the beginning, would not have the interrupt controller. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1066/#review2245 ----------------------------------------------------------- On Feb. 28, 2012, 6:41 a.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1066/ > ----------------------------------------------------------- > > (Updated Feb. 28, 2012, 6:41 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8859:7e91ef576149 > --------------------------- > Fix switching of CPUs > This patch prevents creation of interrupt controller for > cpus that will be switched in later > > > Diffs > ----- > > configs/common/CacheConfig.py c68ae0f78d8e > configs/example/fs.py c68ae0f78d8e > src/cpu/BaseCPU.py c68ae0f78d8e > src/cpu/o3/cpu.cc c68ae0f78d8e > > Diff: http://reviews.gem5.org/r/1066/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
