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Ship it! Ship It! - Ali Saidi On Feb. 29, 2012, 8:55 a.m., Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1031/ > ----------------------------------------------------------- > > (Updated Feb. 29, 2012, 8:55 a.m.) > > > Review request for Default. > > > Description > ------- > > CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable > > Enables the CheckerCPU to be enabled at runtime with the --checker option > from the configs/example/fs.py and configs/example/se.py configuration > files. Also merges with the SE/FS changes. > > > Diffs > ----- > > SConstruct 56d011130987 > configs/common/Options.py 56d011130987 > configs/common/Simulation.py 56d011130987 > configs/example/fs.py 56d011130987 > configs/example/se.py 56d011130987 > src/arch/SConscript 56d011130987 > src/arch/arm/isa.cc 56d011130987 > src/arch/arm/utility.cc 56d011130987 > src/cpu/BaseCPU.py 56d011130987 > src/cpu/SConscript 56d011130987 > src/cpu/base.cc 56d011130987 > src/cpu/base_dyn_inst.hh 56d011130987 > src/cpu/base_dyn_inst_impl.hh 56d011130987 > src/cpu/checker/cpu.hh 56d011130987 > src/cpu/checker/cpu.cc 56d011130987 > src/cpu/checker/cpu_impl.hh 56d011130987 > src/cpu/checker/thread_context.hh 56d011130987 > src/cpu/o3/O3CPU.py 56d011130987 > src/cpu/o3/SConscript 56d011130987 > src/cpu/o3/commit_impl.hh 56d011130987 > src/cpu/o3/cpu.hh 56d011130987 > src/cpu/o3/cpu.cc 56d011130987 > src/cpu/o3/cpu_builder.cc 56d011130987 > src/cpu/o3/dyn_inst_impl.hh 56d011130987 > src/cpu/o3/fetch_impl.hh 56d011130987 > src/cpu/o3/iew_impl.hh 56d011130987 > src/cpu/o3/lsq_unit_impl.hh 56d011130987 > src/cpu/o3/thread_context.hh 56d011130987 > src/cpu/o3/thread_context_impl.hh 56d011130987 > src/cpu/ozone/OzoneCPU.py 56d011130987 > src/cpu/ozone/SConscript 56d011130987 > src/cpu/ozone/cpu_impl.hh 56d011130987 > src/cpu/ozone/front_end_impl.hh 56d011130987 > src/cpu/ozone/lw_back_end_impl.hh 56d011130987 > src/cpu/ozone/lw_lsq_impl.hh 56d011130987 > src/cpu/simple/BaseSimpleCPU.py 56d011130987 > src/cpu/simple/base.hh 56d011130987 > src/cpu/simple/base.cc 56d011130987 > src/cpu/simple_thread.hh 56d011130987 > src/cpu/thread_context.hh 56d011130987 > > Diff: http://reviews.gem5.org/r/1031/diff/ > > > Testing > ------- > > Compiles with ARM ISA. > Boots linux with O3 model attached to Checker in FS mode. > Runs simple HelloWorld in SE mode. > > > Thanks, > > Geoffrey Blake > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
