changeset 44f8e7bb7fdf in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=44f8e7bb7fdf
description:
CPU: Check that the interrupt controller is created when needed
This patch adds a creation-time check to the CPU to ensure that the
interrupt controller is created for the cases where it is needed,
i.e. if the CPU is not being switched in later and not a checker CPU.
The patch also adds the "createInterruptController" call to a number
of the regression scripts.
diffstat:
src/cpu/base.cc | 17 ++++++++++++-----
src/cpu/base.hh | 2 +-
src/cpu/checker/cpu.cc | 2 +-
src/cpu/inorder/cpu.cc | 6 ++++++
src/cpu/o3/cpu.cc | 6 ++++++
tests/configs/inorder-timing.py | 2 ++
tests/configs/o3-timing-mp-ruby.py | 2 ++
tests/configs/o3-timing-mp.py | 2 ++
tests/configs/o3-timing-ruby.py | 2 ++
tests/configs/o3-timing.py | 2 ++
tests/configs/pc-o3-timing.py | 2 ++
tests/configs/pc-simple-atomic.py | 2 ++
tests/configs/pc-simple-timing.py | 2 ++
tests/configs/realview-o3-dual.py | 2 ++
tests/configs/realview-o3.py | 2 ++
tests/configs/realview-simple-atomic-dual.py | 2 ++
tests/configs/realview-simple-atomic.py | 2 ++
tests/configs/realview-simple-timing-dual.py | 2 ++
tests/configs/realview-simple-timing.py | 2 ++
tests/configs/simple-atomic-mp.py | 2 ++
tests/configs/simple-atomic.py | 2 ++
tests/configs/simple-timing-mp.py | 2 ++
tests/configs/simple-timing-ruby.py | 3 +++
tests/configs/simple-timing.py | 2 ++
tests/configs/tsunami-o3-dual.py | 2 ++
tests/configs/tsunami-o3.py | 2 ++
tests/configs/tsunami-simple-atomic-dual.py | 2 ++
tests/configs/tsunami-simple-atomic.py | 2 ++
tests/configs/tsunami-simple-timing-dual.py | 2 ++
tests/configs/tsunami-simple-timing.py | 2 ++
tests/configs/twosys-tsunami-simple-atomic.py | 4 ++++
31 files changed, 81 insertions(+), 7 deletions(-)
diffs (truncated from 412 to 300 lines):
diff -r ad681c92b07d -r 44f8e7bb7fdf src/cpu/base.cc
--- a/src/cpu/base.cc Fri Mar 02 09:18:50 2012 -0500
+++ b/src/cpu/base.cc Fri Mar 02 09:21:48 2012 -0500
@@ -118,7 +118,7 @@
return "CPU Progress";
}
-BaseCPU::BaseCPU(Params *p)
+BaseCPU::BaseCPU(Params *p, bool is_checker)
: MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
_instMasterId(p->system->getMasterId(name() + ".inst")),
_dataMasterId(p->system->getMasterId(name() + ".data")),
@@ -219,10 +219,17 @@
schedule(event, p->function_trace_start);
}
}
- // Check if CPU model has interrupts connected. The CheckerCPU
- // cannot take interrupts directly for example.
- if (interrupts)
- interrupts->setCPU(this);
+
+ // The interrupts should always be present unless this CPU is
+ // switched in later or in case it is a checker CPU
+ if (!params()->defer_registration && !is_checker) {
+ if (interrupts) {
+ interrupts->setCPU(this);
+ } else {
+ fatal("CPU %s has no interrupt controller.\n"
+ "Ensure createInterruptController() is called.\n", name());
+ }
+ }
if (FullSystem) {
profileEvent = NULL;
diff -r ad681c92b07d -r 44f8e7bb7fdf src/cpu/base.hh
--- a/src/cpu/base.hh Fri Mar 02 09:18:50 2012 -0500
+++ b/src/cpu/base.hh Fri Mar 02 09:21:48 2012 -0500
@@ -302,7 +302,7 @@
typedef BaseCPUParams Params;
const Params *params() const
{ return reinterpret_cast<const Params *>(_params); }
- BaseCPU(Params *params);
+ BaseCPU(Params *params, bool is_checker = false);
virtual ~BaseCPU();
virtual void init();
diff -r ad681c92b07d -r 44f8e7bb7fdf src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc Fri Mar 02 09:18:50 2012 -0500
+++ b/src/cpu/checker/cpu.cc Fri Mar 02 09:21:48 2012 -0500
@@ -64,7 +64,7 @@
}
CheckerCPU::CheckerCPU(Params *p)
- : BaseCPU(p), thread(NULL), tc(NULL)
+ : BaseCPU(p, true), thread(NULL), tc(NULL)
{
memReq = NULL;
curStaticInst = NULL;
diff -r ad681c92b07d -r 44f8e7bb7fdf src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Fri Mar 02 09:18:50 2012 -0500
+++ b/src/cpu/inorder/cpu.cc Fri Mar 02 09:21:48 2012 -0500
@@ -387,6 +387,12 @@
}
+ // InOrderCPU always requires an interrupt controller.
+ if (!params->defer_registration && !interrupts) {
+ fatal("InOrderCPU %s has no interrupt controller.\n"
+ "Ensure createInterruptController() is called.\n", name());
+ }
+
dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
dummyReqInst->setSquashed();
dummyReqInst->resetInstCount();
diff -r ad681c92b07d -r 44f8e7bb7fdf src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Fri Mar 02 09:18:50 2012 -0500
+++ b/src/cpu/o3/cpu.cc Fri Mar 02 09:21:48 2012 -0500
@@ -460,6 +460,12 @@
this->threadContexts.push_back(tc);
}
+ // FullO3CPU always requires an interrupt controller.
+ if (!params->defer_registration && !interrupts) {
+ fatal("FullO3CPU %s has no interrupt controller.\n"
+ "Ensure createInterruptController() is called.\n", name());
+ }
+
for (ThreadID tid = 0; tid < this->numThreads; tid++)
this->thread[tid]->setFuncExeInst(0);
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/inorder-timing.py Fri Mar 02 09:21:48 2012 -0500
@@ -52,6 +52,8 @@
membus = Bus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
root = Root(full_system = False, system = system)
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/o3-timing-mp-ruby.py
--- a/tests/configs/o3-timing-mp-ruby.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/o3-timing-mp-ruby.py Fri Mar 02 09:21:48 2012 -0500
@@ -40,6 +40,8 @@
system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
for cpu in cpus:
+ # create the interrupt controller
+ cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/o3-timing-mp.py Fri Mar 02 09:21:48 2012 -0500
@@ -71,6 +71,8 @@
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
+ # create the interrupt controller
+ cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/o3-timing-ruby.py
--- a/tests/configs/o3-timing-ruby.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/o3-timing-ruby.py Fri Mar 02 09:21:48 2012 -0500
@@ -41,6 +41,8 @@
physmem = ruby_memory,
membus = Bus())
system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
# Connect the system port for loading of binaries etc
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/o3-timing.py Fri Mar 02 09:21:48 2012 -0500
@@ -52,6 +52,8 @@
membus = Bus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
root = Root(full_system = False, system = system)
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/pc-o3-timing.py
--- a/tests/configs/pc-o3-timing.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/pc-o3-timing.py Fri Mar 02 09:21:48 2012 -0500
@@ -104,6 +104,8 @@
L1(size = '32kB', assoc = 4),
PageTableWalkerCache(),
PageTableWalkerCache())
+# create the interrupt controller
+cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/pc-simple-atomic.py
--- a/tests/configs/pc-simple-atomic.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/pc-simple-atomic.py Fri Mar 02 09:21:48 2012 -0500
@@ -106,6 +106,8 @@
L1(size = '32kB', assoc = 4),
PageTableWalkerCache(),
PageTableWalkerCache())
+# create the interrupt controller
+cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/pc-simple-timing.py
--- a/tests/configs/pc-simple-timing.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/pc-simple-timing.py Fri Mar 02 09:21:48 2012 -0500
@@ -106,6 +106,8 @@
L1(size = '32kB', assoc = 4),
PageTableWalkerCache(),
PageTableWalkerCache())
+# create the interrupt controller
+cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/realview-o3-dual.py
--- a/tests/configs/realview-o3-dual.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/realview-o3-dual.py Fri Mar 02 09:21:48 2012 -0500
@@ -88,6 +88,8 @@
for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
+ # create the interrupt controller
+ c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/realview-o3.py
--- a/tests/configs/realview-o3.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/realview-o3.py Fri Mar 02 09:21:48 2012 -0500
@@ -88,6 +88,8 @@
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf
tests/configs/realview-simple-atomic-dual.py
--- a/tests/configs/realview-simple-atomic-dual.py Fri Mar 02 09:18:50
2012 -0500
+++ b/tests/configs/realview-simple-atomic-dual.py Fri Mar 02 09:21:48
2012 -0500
@@ -88,6 +88,8 @@
for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
+ # create the interrupt controller
+ c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/realview-simple-atomic.py
--- a/tests/configs/realview-simple-atomic.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/realview-simple-atomic.py Fri Mar 02 09:21:48 2012 -0500
@@ -86,6 +86,8 @@
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf
tests/configs/realview-simple-timing-dual.py
--- a/tests/configs/realview-simple-timing-dual.py Fri Mar 02 09:18:50
2012 -0500
+++ b/tests/configs/realview-simple-timing-dual.py Fri Mar 02 09:21:48
2012 -0500
@@ -88,6 +88,8 @@
for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
+ # create the interrupt controller
+ c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/realview-simple-timing.py
--- a/tests/configs/realview-simple-timing.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/realview-simple-timing.py Fri Mar 02 09:21:48 2012 -0500
@@ -88,6 +88,8 @@
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/simple-atomic-mp.py
--- a/tests/configs/simple-atomic-mp.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/simple-atomic-mp.py Fri Mar 02 09:21:48 2012 -0500
@@ -70,6 +70,8 @@
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
+ # create the interrupt controller
+ cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/simple-atomic.py
--- a/tests/configs/simple-atomic.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/simple-atomic.py Fri Mar 02 09:21:48 2012 -0500
@@ -34,6 +34,8 @@
membus = Bus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
+# create the interrupt controller
+system.cpu.createInterruptController()
system.cpu.connectAllPorts(system.membus)
system.cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/simple-timing-mp.py
--- a/tests/configs/simple-timing-mp.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/simple-timing-mp.py Fri Mar 02 09:21:48 2012 -0500
@@ -70,6 +70,8 @@
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
+ # create the interrupt controller
+ cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
diff -r ad681c92b07d -r 44f8e7bb7fdf tests/configs/simple-timing-ruby.py
--- a/tests/configs/simple-timing-ruby.py Fri Mar 02 09:18:50 2012 -0500
+++ b/tests/configs/simple-timing-ruby.py Fri Mar 02 09:21:48 2012 -0500
@@ -75,6 +75,9 @@
assert(len(system.ruby._cpu_ruby_ports) == 1)
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