changeset 2e38fd9937a9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2e38fd9937a9
description:
CheckerCPU: Make some basic regression tests for CheckerCPU
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
diffstat:
tests/SConscript |
5 +-
tests/configs/o3-timing-checker.py |
68 +
tests/configs/realview-o3-checker.py |
109 +
tests/configs/simple-atomic-dummychecker.py |
51 +
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini |
1059 ++++++++++
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr |
25 +
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout |
15 +
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt |
881 ++++++++
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini |
607 +++++
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr |
2 +
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout |
11 +
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt |
676 ++++++
tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini |
188 +
tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr |
2 +
tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout |
11 +
tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt |
135 +
tests/quick/se/00.hello/test.py |
2 +
17 files changed, 3846 insertions(+), 1 deletions(-)
diffs (truncated from 3928 to 300 lines):
diff -r befcf4d79fc1 -r 2e38fd9937a9 tests/SConscript
--- a/tests/SConscript Fri Mar 09 09:59:28 2012 -0500
+++ b/tests/SConscript Fri Mar 09 09:59:28 2012 -0500
@@ -277,11 +277,14 @@
configs += ['t1000-simple-atomic',
't1000-simple-timing']
if env['TARGET_ISA'] == 'arm':
- configs += ['realview-simple-atomic',
+ configs += ['simple-atomic-dummychecker',
+ 'o3-timing-checker',
+ 'realview-simple-atomic',
'realview-simple-atomic-dual',
'realview-simple-timing',
'realview-simple-timing-dual',
'realview-o3',
+ 'realview-o3-checker',
'realview-o3-dual']
if env['TARGET_ISA'] == 'x86':
configs += ['pc-simple-atomic',
diff -r befcf4d79fc1 -r 2e38fd9937a9 tests/configs/o3-timing-checker.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/o3-timing-checker.py Fri Mar 09 09:59:28 2012 -0500
@@ -0,0 +1,68 @@
+# Copyright (c) 2011 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Geoffrey Blake
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+
+class MyCache(BaseCache):
+ assoc = 2
+ block_size = 64
+ latency = '1ns'
+ mshrs = 10
+ tgts_per_mshr = 5
+
+class MyL1Cache(MyCache):
+ is_top_level = True
+ tgts_per_mshr = 20
+
+cpu = DerivO3CPU(cpu_id=0)
+cpu.createInterruptController()
+cpu.addCheckerCpu()
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+ MyL1Cache(size = '256kB'),
+ MyCache(size = '2MB'))
+cpu.clock = '2GHz'
+
+system = System(cpu = cpu,
+ physmem = PhysicalMemory(),
+ membus = Bus())
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+cpu.connectAllPorts(system.membus)
+
+root = Root(full_system = False, system = system)
diff -r befcf4d79fc1 -r 2e38fd9937a9 tests/configs/realview-o3-checker.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/realview-o3-checker.py Fri Mar 09 09:59:28 2012 -0500
@@ -0,0 +1,109 @@
+# Copyright (c) 2011 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Geoffrey Blake
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 20
+ is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ addr_ranges = [AddrRange(0, size='256MB')]
+ forward_snoops = False
+
+#cpu
+cpu = DerivO3CPU(cpu_id=0)
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
+
+#connect up the checker
+cpu.addCheckerCpu()
+#connect up the cpu and l1s
+cpu.createInterruptController()
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(full_system=True, system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
diff -r befcf4d79fc1 -r 2e38fd9937a9 tests/configs/simple-atomic-dummychecker.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/simple-atomic-dummychecker.py Fri Mar 09 09:59:28
2012 -0500
@@ -0,0 +1,51 @@
+# Copyright (c) 2011 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Geoffrey Blake
+
+import m5
+from m5.objects import *
+
+system = System(cpu = AtomicSimpleCPU(cpu_id=0),
+ physmem = PhysicalMemory(),
+ membus = Bus())
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+system.cpu.addCheckerCpu()
+system.cpu.createInterruptController()
+system.cpu.connectAllPorts(system.membus)
+system.cpu.clock = '2GHz'
+
+root = Root(full_system = False, system = system)
diff -r befcf4d79fc1 -r 2e38fd9937a9
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
Fri Mar 09 09:59:28 2012 -0500
@@ -0,0 +1,1059 @@
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview
terminal toL2Bus vncserver
+atags_addr=256
+boot_loader=/dist/m5/system/binaries/boot.arm
+boot_loader_mem=system.realview.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8
mem=128MB root=/dev/sda1
+flags_addr=268435504
+gic_cpu_addr=520093952
+init_param=0
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=timing
+memories=system.physmem system.realview.nvmem
+midr_regval=890224640
+num_work_ids=16
+physmem=system.physmem
+readfile=tests/halt.sh
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
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