changeset a16ba72db7d0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a16ba72db7d0
description:
Power: Change bitfield name to avoid conflicts with range_map
This patch changes the name of a bitfield from W to W_FIELD to avoid
clashes with W being used as a class (typename) in the templatized
range_map. It also changes L to L_FIELD to avoid future problems. The
problem manifestes itself when the CPU includes a header that in turn
includes range_map.hh. The relevant parts of the decoder are updated.
diffstat:
src/arch/power/isa/bitfields.isa | 6 ++++--
src/arch/power/isa/decoder.isa | 7 ++++---
2 files changed, 8 insertions(+), 5 deletions(-)
diffs (38 lines):
diff -r 7d95b650c9b6 -r a16ba72db7d0 src/arch/power/isa/bitfields.isa
--- a/src/arch/power/isa/bitfields.isa Fri Mar 23 06:54:25 2012 -0400
+++ b/src/arch/power/isa/bitfields.isa Mon Mar 26 05:35:24 2012 -0400
@@ -75,8 +75,10 @@
// Fields for FPSCR manipulation instructions
def bitfield FLM <24:17>;
-def bitfield L <25>;
-def bitfield W <16>;
+// Named so to avoid conflicts with potential template typenames
+def bitfield L_FIELD <25>;
+// Named so to avoid conflicts with range_map.hh
+def bitfield W_FIELD <16>;
// Named so to avoid conflicts with range.hh
def bitfield U_FIELD <15:12>;
diff -r 7d95b650c9b6 -r a16ba72db7d0 src/arch/power/isa/decoder.isa
--- a/src/arch/power/isa/decoder.isa Fri Mar 23 06:54:25 2012 -0400
+++ b/src/arch/power/isa/decoder.isa Mon Mar 26 05:35:24 2012 -0400
@@ -571,14 +571,15 @@
}});
583: mffs({{ Ft_uq = FPSCR; }});
134: mtfsfi({{
- FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W)), U_FIELD);
+ FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
+ U_FIELD);
}});
711: mtfsf({{
- if (L == 1) { FPSCR = Fb_uq; }
+ if (L_FIELD == 1) { FPSCR = Fb_uq; }
else {
for (int i = 0; i < 8; ++i) {
if (bits(FLM, i) == 1) {
- int k = 4 * (i + (8 * (1 - W)));
+ int k = 4 * (i + (8 * (1 - W_FIELD)));
FPSCR = insertBits(FPSCR, k, k + 3,
bits(Fb_uq, k, k + 3));
}
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