I have some ideas about how to improve address translation, specifically with an eye towards x86.
1. Use a prefix matching trie to lookup entries in the TLB. Page sizes are always powers of two, and are aligned to multiples of two. A trie that matches an address incrementally would be a pretty efficient way to look things up, I think. 2. Cache translations. This would be similar to but independent of the TLB itself. When an address is looked up, if it was successfully translated in the past, use the trie above to lookup a small specialized object that knows exactly how to translate the address, presupposing all the relevant context. This gets a little weird because of segmentation since segments are NOT aligned to a power of two or sized as a power of two. I've unsuccessfully tried to find some time to work on this for a while, and I'm thinking the best chance it has to get done is to let other folks know about it let them give it a shot. Gabe _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
