changeset 7f36d4436074 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7f36d4436074
description:
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
diffstat:
src/arch/x86/pagetable_walker.cc | 9 +-
src/arch/x86/pagetable_walker.hh | 6 +-
src/cpu/base.cc | 2 +-
src/cpu/base.hh | 2 +-
src/cpu/inorder/cpu.cc | 4 +-
src/cpu/inorder/cpu.hh | 4 +-
src/cpu/inorder/resources/cache_unit.cc | 2 +-
src/cpu/o3/cpu.cc | 15 +-
src/cpu/o3/cpu.hh | 8 +-
src/cpu/o3/fetch_impl.hh | 4 +-
src/cpu/o3/lsq.hh | 4 +-
src/cpu/o3/lsq_impl.hh | 11 +-
src/cpu/o3/lsq_unit.hh | 4 +-
src/cpu/o3/lsq_unit_impl.hh | 4 +-
src/cpu/simple/timing.cc | 22 +-
src/cpu/simple/timing.hh | 6 +-
src/cpu/testers/directedtest/InvalidateGenerator.cc | 2 +-
src/cpu/testers/directedtest/RubyDirectedTester.cc | 2 +-
src/cpu/testers/directedtest/RubyDirectedTester.hh | 2 +-
src/cpu/testers/directedtest/SeriesRequestGenerator.cc | 2 +-
src/cpu/testers/memtest/memtest.cc | 7 +-
src/cpu/testers/memtest/memtest.hh | 4 +-
src/cpu/testers/networktest/networktest.cc | 7 +-
src/cpu/testers/networktest/networktest.hh | 2 +-
src/cpu/testers/rubytest/Check.cc | 8 +-
src/cpu/testers/rubytest/RubyTester.cc | 2 +-
src/cpu/testers/rubytest/RubyTester.hh | 2 +-
src/dev/io_device.cc | 7 +-
src/dev/io_device.hh | 5 +-
src/mem/bridge.cc | 15 +-
src/mem/bridge.hh | 4 +-
src/mem/bus.cc | 318 ++++++++--------
src/mem/bus.hh | 32 +-
src/mem/cache/base.hh | 4 +-
src/mem/cache/cache.hh | 14 +-
src/mem/cache/cache_impl.hh | 28 +-
src/mem/mport.hh | 4 +-
src/mem/packet_queue.cc | 44 +-
src/mem/packet_queue.hh | 88 +++-
src/mem/port.cc | 32 +
src/mem/port.hh | 187 +++++----
src/mem/qport.hh | 8 +-
src/mem/ruby/system/RubyPort.cc | 11 +-
src/mem/ruby/system/RubyPort.hh | 8 +-
src/mem/tport.cc | 6 +-
src/mem/tport.hh | 8 +-
src/sim/system.hh | 2 +-
47 files changed, 547 insertions(+), 425 deletions(-)
diffs (truncated from 2155 to 300 lines):
diff -r fe542ba8a878 -r 7f36d4436074 src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc Mon Apr 30 03:47:22 2012 -0500
+++ b/src/arch/x86/pagetable_walker.cc Tue May 01 13:40:42 2012 -0400
@@ -114,15 +114,14 @@
}
bool
-Walker::WalkerPort::recvTiming(PacketPtr pkt)
+Walker::WalkerPort::recvTimingResp(PacketPtr pkt)
{
- return walker->recvTiming(pkt);
+ return walker->recvTimingResp(pkt);
}
bool
-Walker::recvTiming(PacketPtr pkt)
+Walker::recvTimingResp(PacketPtr pkt)
{
- assert(pkt->isResponse());
WalkerSenderState * senderState =
dynamic_cast<WalkerSenderState *>(pkt->senderState);
pkt->senderState = senderState->saved;
@@ -171,7 +170,7 @@
bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt)
{
pkt->senderState = new WalkerSenderState(sendingState, pkt->senderState);
- return port.sendTiming(pkt);
+ return port.sendTimingReq(pkt);
}
MasterPort &
diff -r fe542ba8a878 -r 7f36d4436074 src/arch/x86/pagetable_walker.hh
--- a/src/arch/x86/pagetable_walker.hh Mon Apr 30 03:47:22 2012 -0500
+++ b/src/arch/x86/pagetable_walker.hh Tue May 01 13:40:42 2012 -0400
@@ -70,12 +70,12 @@
protected:
Walker *walker;
- bool recvTiming(PacketPtr pkt);
+ bool recvTimingResp(PacketPtr pkt);
/**
* Snooping a coherence request, do nothing.
*/
- bool recvTimingSnoop(PacketPtr pkt) { return true; }
+ void recvTimingSnoopReq(PacketPtr pkt) { }
Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
void recvFunctionalSnoop(PacketPtr pkt) { }
void recvRetry();
@@ -179,7 +179,7 @@
MasterID masterId;
// Functions for dealing with packets.
- bool recvTiming(PacketPtr pkt);
+ bool recvTimingResp(PacketPtr pkt);
void recvRetry();
bool sendTiming(WalkerState * sendingState, PacketPtr pkt);
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/base.cc
--- a/src/cpu/base.cc Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/base.cc Tue May 01 13:40:42 2012 -0400
@@ -532,7 +532,7 @@
}
bool
-BaseCPU::CpuPort::recvTiming(PacketPtr pkt)
+BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt)
{
panic("BaseCPU doesn't expect recvTiming!\n");
return true;
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/base.hh
--- a/src/cpu/base.hh Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/base.hh Tue May 01 13:40:42 2012 -0400
@@ -133,7 +133,7 @@
protected:
- virtual bool recvTiming(PacketPtr pkt);
+ virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvRetry();
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/inorder/cpu.cc Tue May 01 13:40:42 2012 -0400
@@ -88,10 +88,8 @@
{ }
bool
-InOrderCPU::CachePort::recvTiming(Packet *pkt)
+InOrderCPU::CachePort::recvTimingResp(Packet *pkt)
{
- assert(pkt->isResponse());
-
if (pkt->isError())
DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
pkt->getAddr());
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/inorder/cpu.hh Tue May 01 13:40:42 2012 -0400
@@ -170,13 +170,13 @@
protected:
/** Timing version of receive */
- bool recvTiming(PacketPtr pkt);
+ bool recvTimingResp(PacketPtr pkt);
/** Handles doing a retry of a failed timing request. */
void recvRetry();
/** Ignoring snoops for now. */
- bool recvTimingSnoop(PacketPtr pkt) { return true; }
+ void recvTimingSnoopReq(PacketPtr pkt) { }
};
/** Define TickEvent for the CPU */
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/inorder/resources/cache_unit.cc Tue May 01 13:40:42 2012 -0400
@@ -873,7 +873,7 @@
tid, inst->seqNum, cache_req->dataPkt->getAddr());
if (do_access) {
- if (!cachePort->sendTiming(cache_req->dataPkt)) {
+ if (!cachePort->sendTimingReq(cache_req->dataPkt)) {
DPRINTF(InOrderCachePort,
"[tid:%i] [sn:%i] cannot access cache, because port "
"is blocked. now waiting to retry request\n", tid,
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/o3/cpu.cc Tue May 01 13:40:42 2012 -0400
@@ -87,9 +87,8 @@
template<class Impl>
bool
-FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
+FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
{
- assert(pkt->isResponse());
DPRINTF(O3CPU, "Fetch unit received timing\n");
// We shouldn't ever get a block in ownership state
assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
@@ -107,18 +106,16 @@
template <class Impl>
bool
-FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
+FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
{
- assert(pkt->isResponse());
- return lsq->recvTiming(pkt);
+ return lsq->recvTimingResp(pkt);
}
template <class Impl>
-bool
-FullO3CPU<Impl>::DcachePort::recvTimingSnoop(PacketPtr pkt)
+void
+FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
{
- assert(pkt->isRequest());
- return lsq->recvTimingSnoop(pkt);
+ lsq->recvTimingSnoopReq(pkt);
}
template <class Impl>
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/o3/cpu.hh Tue May 01 13:40:42 2012 -0400
@@ -148,8 +148,8 @@
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
- virtual bool recvTiming(PacketPtr pkt);
- virtual bool recvTimingSnoop(PacketPtr pkt) { return true; }
+ virtual bool recvTimingResp(PacketPtr pkt);
+ virtual void recvTimingSnoopReq(PacketPtr pkt) { }
/** Handles doing a retry of a failed fetch. */
virtual void recvRetry();
@@ -176,8 +176,8 @@
/** Timing version of receive. Handles writing back and
* completing the load or store that has returned from
* memory. */
- virtual bool recvTiming(PacketPtr pkt);
- virtual bool recvTimingSnoop(PacketPtr pkt);
+ virtual bool recvTimingResp(PacketPtr pkt);
+ virtual void recvTimingSnoopReq(PacketPtr pkt);
/** Handles doing a retry of the previous send. */
virtual void recvRetry();
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/o3/fetch_impl.hh Tue May 01 13:40:42 2012 -0400
@@ -621,7 +621,7 @@
fetchedCacheLines++;
// Access the cache.
- if (!cpu->getInstPort().sendTiming(data_pkt)) {
+ if (!cpu->getInstPort().sendTimingReq(data_pkt)) {
assert(retryPkt == NULL);
assert(retryTid == InvalidThreadID);
DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
@@ -1356,7 +1356,7 @@
assert(retryTid != InvalidThreadID);
assert(fetchStatus[retryTid] == IcacheWaitRetry);
- if (cpu->getInstPort().sendTiming(retryPkt)) {
+ if (cpu->getInstPort().sendTimingReq(retryPkt)) {
fetchStatus[retryTid] = IcacheWaitResponse;
retryPkt = NULL;
retryTid = InvalidThreadID;
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/o3/lsq.hh
--- a/src/cpu/o3/lsq.hh Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/o3/lsq.hh Tue May 01 13:40:42 2012 -0400
@@ -297,9 +297,9 @@
*
* @param pkt Response packet from the memory sub-system
*/
- bool recvTiming(PacketPtr pkt);
+ bool recvTimingResp(PacketPtr pkt);
- bool recvTimingSnoop(PacketPtr pkt);
+ void recvTimingSnoopReq(PacketPtr pkt);
/** The CPU pointer. */
O3CPU *cpu;
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/o3/lsq_impl.hh
--- a/src/cpu/o3/lsq_impl.hh Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/o3/lsq_impl.hh Tue May 01 13:40:42 2012 -0400
@@ -319,9 +319,8 @@
template <class Impl>
bool
-LSQ<Impl>::recvTiming(PacketPtr pkt)
+LSQ<Impl>::recvTimingResp(PacketPtr pkt)
{
- assert(pkt->isResponse());
if (pkt->isError())
DPRINTF(LSQ, "Got error packet back for address: %#X\n",
pkt->getAddr());
@@ -330,10 +329,9 @@
}
template <class Impl>
-bool
-LSQ<Impl>::recvTimingSnoop(PacketPtr pkt)
+void
+LSQ<Impl>::recvTimingSnoopReq(PacketPtr pkt)
{
- assert(pkt->isRequest());
DPRINTF(LSQ, "received pkt for addr:%#x %s\n", pkt->getAddr(),
pkt->cmdString());
@@ -345,9 +343,6 @@
thread[tid].checkSnoop(pkt);
}
}
-
- // to provide stronger consistency model
- return true;
}
template<class Impl>
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/o3/lsq_unit.hh Tue May 01 13:40:42 2012 -0400
@@ -801,7 +801,7 @@
state->mainPkt = data_pkt;
}
- if (!dcachePort->sendTiming(fst_data_pkt)) {
+ if (!dcachePort->sendTimingReq(fst_data_pkt)) {
// Delete state and data packet because a load retry
// initiates a pipeline restart; it does not retry.
delete state;
@@ -830,7 +830,7 @@
// The first packet will return in completeDataAccess and be
// handled there.
++usedPorts;
- if (!dcachePort->sendTiming(snd_data_pkt)) {
+ if (!dcachePort->sendTimingReq(snd_data_pkt)) {
// The main packet will be deleted in completeDataAccess.
delete snd_data_pkt->req;
diff -r fe542ba8a878 -r 7f36d4436074 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Mon Apr 30 03:47:22 2012 -0500
+++ b/src/cpu/o3/lsq_unit_impl.hh Tue May 01 13:40:42 2012 -0400
@@ -1180,7 +1180,7 @@
bool
LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
{
- if (!dcachePort->sendTiming(data_pkt)) {
+ if (!dcachePort->sendTimingReq(data_pkt)) {
// Need to handle becoming blocked on a store.
isStoreBlocked = true;
++lsqCacheBlocked;
@@ -1203,7 +1203,7 @@
LSQSenderState *state =
dynamic_cast<LSQSenderState *>(retryPkt->senderState);
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