changeset e9201a7bce59 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e9201a7bce59
description:
CPU: Merge the predecoder and decoder.
These classes are always used together, and merging them will give the
ISAs
more flexibility in how they cache things and manage the process.
diffstat:
src/arch/SConscript | 1 -
src/arch/alpha/decoder.hh | 66 ++++
src/arch/alpha/isa/main.isa | 1 +
src/arch/alpha/predecoder.hh | 113 -------
src/arch/arm/SConscript | 5 +-
src/arch/arm/decoder.cc | 88 +++++-
src/arch/arm/decoder.hh | 103 ++++++-
src/arch/arm/predecoder.cc | 135 --------
src/arch/arm/predecoder.hh | 154 ---------
src/arch/arm/types.hh | 6 +-
src/arch/mips/decoder.hh | 68 ++++-
src/arch/mips/predecoder.hh | 110 ------
src/arch/power/decoder.hh | 72 ++++
src/arch/power/predecoder.hh | 125 -------
src/arch/sparc/decoder.hh | 76 ++++
src/arch/sparc/predecoder.hh | 121 -------
src/arch/x86/SConscript | 5 +-
src/arch/x86/decoder.cc | 375 +++++++++++++++++++++++
src/arch/x86/decoder.hh | 189 +++++++++++-
src/arch/x86/decoder_tables.cc | 204 ++++++++++++
src/arch/x86/emulenv.cc | 2 +-
src/arch/x86/isa/decoder/one_byte_opcodes.isa | 2 +-
src/arch/x86/predecoder.cc | 419 --------------------------
src/arch/x86/predecoder.hh | 239 --------------
src/arch/x86/predecoder_tables.cc | 204 ------------
src/arch/x86/types.hh | 4 +-
src/cpu/base.hh | 6 -
src/cpu/checker/cpu.hh | 8 +-
src/cpu/checker/cpu_impl.hh | 38 +-
src/cpu/inorder/cpu.cc | 4 +-
src/cpu/inorder/cpu.hh | 2 +-
src/cpu/inorder/resources/cache_unit.cc | 1 -
src/cpu/inorder/resources/cache_unit.hh | 1 -
src/cpu/inorder/resources/fetch_unit.cc | 16 +-
src/cpu/inorder/resources/fetch_unit.hh | 5 +-
src/cpu/inorder/thread_context.hh | 6 +-
src/cpu/legiontrace.cc | 13 +-
src/cpu/o3/fetch.hh | 6 +-
src/cpu/o3/fetch_impl.hh | 28 +-
src/cpu/o3/thread_context.hh | 6 +-
src/cpu/simple/atomic.cc | 4 +-
src/cpu/simple/base.cc | 23 +-
src/cpu/simple/base.hh | 6 -
src/cpu/simple_thread.cc | 7 +-
44 files changed, 1320 insertions(+), 1747 deletions(-)
diffs (truncated from 3844 to 300 lines):
diff -r bb25e7646c41 -r e9201a7bce59 src/arch/SConscript
--- a/src/arch/SConscript Fri May 25 00:55:24 2012 -0700
+++ b/src/arch/SConscript Sat May 26 13:44:46 2012 -0700
@@ -54,7 +54,6 @@
mmapped_ipr.hh
mt.hh
process.hh
- predecoder.hh
registers.hh
remote_gdb.hh
stacktrace.hh
diff -r bb25e7646c41 -r e9201a7bce59 src/arch/alpha/decoder.hh
--- a/src/arch/alpha/decoder.hh Fri May 25 00:55:24 2012 -0700
+++ b/src/arch/alpha/decoder.hh Sat May 26 13:44:46 2012 -0700
@@ -34,6 +34,7 @@
#include "arch/types.hh"
#include "cpu/decode_cache.hh"
#include "cpu/static_inst_fwd.hh"
+#include "sim/full_system.hh"
namespace AlphaISA
{
@@ -41,6 +42,62 @@
class Decoder
{
protected:
+ ThreadContext *tc;
+
+ // The extended machine instruction being generated
+ ExtMachInst ext_inst;
+ bool instDone;
+
+ public:
+ Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+ {}
+
+ ThreadContext *
+ getTC()
+ {
+ return tc;
+ }
+
+ void
+ setTC(ThreadContext * _tc)
+ {
+ tc = _tc;
+ }
+
+ void
+ process()
+ { }
+
+ void
+ reset()
+ {
+ instDone = false;
+ }
+
+ // Use this to give data to the predecoder. This should be used
+ // when there is control flow.
+ void
+ moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
+ {
+ ext_inst = inst;
+ instDone = true;
+ if (FullSystem)
+ ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
+ }
+
+ bool
+ needMoreBytes()
+ {
+ return true;
+ }
+
+ bool
+ instReady()
+ {
+ return instDone;
+ }
+
+ protected:
/// A cache of decoded instruction objects.
static DecodeCache defaultCache;
@@ -55,6 +112,15 @@
{
return defaultCache.decode(this, mach_inst, addr);
}
+
+ StaticInstPtr
+ decode(AlphaISA::PCState &nextPC)
+ {
+ if (!instDone)
+ return NULL;
+ instDone = false;
+ return decode(ext_inst, nextPC.instAddr());
+ }
};
} // namespace AlphaISA
diff -r bb25e7646c41 -r e9201a7bce59 src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa Fri May 25 00:55:24 2012 -0700
+++ b/src/arch/alpha/isa/main.isa Sat May 26 13:44:46 2012 -0700
@@ -73,6 +73,7 @@
output exec {{
#include <cmath>
+#include "arch/alpha/decoder.hh"
#include "arch/alpha/registers.hh"
#include "arch/alpha/regredir.hh"
#include "arch/generic/memhelpers.hh"
diff -r bb25e7646c41 -r e9201a7bce59 src/arch/alpha/predecoder.hh
--- a/src/arch/alpha/predecoder.hh Fri May 25 00:55:24 2012 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_PREDECODER_HH__
-#define __ARCH_ALPHA_PREDECODER_HH__
-
-#include "arch/alpha/types.hh"
-#include "base/misc.hh"
-#include "base/types.hh"
-#include "sim/full_system.hh"
-
-class ThreadContext;
-
-namespace AlphaISA {
-
-class Predecoder
-{
- protected:
- ThreadContext *tc;
-
- // The extended machine instruction being generated
- ExtMachInst ext_inst;
- bool emiIsReady;
-
- public:
- Predecoder(ThreadContext * _tc)
- : tc(_tc), emiIsReady(false)
- {}
-
- ThreadContext *
- getTC()
- {
- return tc;
- }
-
- void
- setTC(ThreadContext * _tc)
- {
- tc = _tc;
- }
-
- void
- process()
- { }
-
- void
- reset()
- {
- emiIsReady = false;
- }
-
- // Use this to give data to the predecoder. This should be used
- // when there is control flow.
- void
- moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
- {
- ext_inst = inst;
- emiIsReady = true;
- if (FullSystem)
- ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
- }
-
- bool
- needMoreBytes()
- {
- return true;
- }
-
- bool
- extMachInstReady()
- {
- return emiIsReady;
- }
-
- // This returns a constant reference to the ExtMachInst to avoid a copy
- const ExtMachInst &
- getExtMachInst(PCState &pc)
- {
- emiIsReady = false;
- return ext_inst;
- }
-};
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_PREDECODER_HH__
diff -r bb25e7646c41 -r e9201a7bce59 src/arch/arm/SConscript
--- a/src/arch/arm/SConscript Fri May 25 00:55:24 2012 -0700
+++ b/src/arch/arm/SConscript Sat May 26 13:44:46 2012 -0700
@@ -62,7 +62,6 @@
Source('linux/system.cc')
Source('miscregs.cc')
Source('nativetrace.cc')
- Source('predecoder.cc')
Source('process.cc')
Source('remote_gdb.cc')
Source('stacktrace.cc')
@@ -78,9 +77,9 @@
SimObject('ArmTLB.py')
DebugFlag('Arm')
+ DebugFlag('Decoder', "Instructions returned by the predecoder")
+ DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
DebugFlag('TLBVerbose')
- DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
- DebugFlag('Predecoder', "Instructions returned by the predecoder")
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
diff -r bb25e7646c41 -r e9201a7bce59 src/arch/arm/decoder.cc
--- a/src/arch/arm/decoder.cc Fri May 25 00:55:24 2012 -0700
+++ b/src/arch/arm/decoder.cc Sat May 26 13:44:46 2012 -0700
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 Google
+ * Copyright (c) 2012 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,10 +29,96 @@
*/
#include "arch/arm/decoder.hh"
+#include "arch/arm/isa_traits.hh"
+#include "arch/arm/utility.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "debug/Decoder.hh"
namespace ArmISA
{
DecodeCache Decoder::defaultCache;
+void
+Decoder::process()
+{
+ // emi is typically ready, with some caveats below...
+ instDone = true;
+
+ if (!emi.thumb) {
+ emi.instBits = data;
+ emi.sevenAndFour = bits(data, 7) && bits(data, 4);
+ emi.isMisc = (bits(data, 24, 23) == 0x2 &&
+ bits(data, 20) == 0);
+ consumeBytes(4);
+ DPRINTF(Decoder, "Arm inst: %#x.\n", (uint64_t)emi);
+ } else {
+ uint16_t word = (data >> (offset * 8));
+ if (bigThumb) {
+ // A 32 bit thumb inst is half collected.
+ emi.instBits = emi.instBits | word;
+ bigThumb = false;
+ consumeBytes(2);
+ DPRINTF(Decoder, "Second half of 32 bit Thumb: %#x.\n",
+ emi.instBits);
+ } else {
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