changeset 1e783db0f3af in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1e783db0f3af
description:
Stats: Fix stats to match output after changeset 8800b05e1cb3
This patch updates the stats for parser to be aligned with the most
up-to-date behaviour. Somehow the wrong results got committed as part
of 8800b05e1cb3 (see details below) when fixing the no_value -> nan
stats.
changeset: 8983:8800b05e1cb3
user: Nathan Binkert <[email protected]>
summary: stats: update stats for no_value -> nan
diffstat:
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | 1104 ++++++------
1 files changed, 552 insertions(+), 552 deletions(-)
diffs (truncated from 1185 to 300 lines):
diff -r 8b9f227b64d8 -r 1e783db0f3af
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt Wed May 30
05:31:48 2012 -0400
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt Wed May 09
11:52:14 2012 -0700
@@ -1,26 +1,26 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.233090 #
Number of seconds simulated
-sim_ticks 233090215000 #
Number of ticks simulated
-final_tick 233090215000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 0.233058 #
Number of seconds simulated
+sim_ticks 233057542500 #
Number of ticks simulated
+final_tick 233057542500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 75004 #
Simulator instruction rate (inst/s)
-host_op_rate 84493 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34350324 #
Simulator tick rate (ticks/s)
-host_mem_usage 237136 #
Number of bytes of host memory used
-host_seconds 6785.68 #
Real time elapsed on the host
-sim_insts 508954971 #
Number of instructions simulated
-sim_ops 573341532 #
Number of ops (including micro ops) simulated
-system.physmem.bytes_read 15203328 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read 248448 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written 10942400 #
Number of bytes written to this memory
-system.physmem.num_reads 237552 #
Number of read requests responded to by this memory
-system.physmem.num_writes 170975 #
Number of write requests responded to by this memory
+host_inst_rate 104599 #
Simulator instruction rate (inst/s)
+host_op_rate 117832 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47897344 #
Simulator tick rate (ticks/s)
+host_mem_usage 237516 #
Number of bytes of host memory used
+host_seconds 4865.77 #
Real time elapsed on the host
+sim_insts 508954936 #
Number of instructions simulated
+sim_ops 573341497 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read 15214144 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read 246208 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written 10947904 #
Number of bytes written to this memory
+system.physmem.num_reads 237721 #
Number of read requests responded to by this memory
+system.physmem.num_writes 171061 #
Number of write requests responded to by this memory
system.physmem.num_other 0 #
Number of other requests responded to by this memory
-system.physmem.bw_read 65225080 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1065888 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 46944914 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 112169994 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 65280633 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1056426 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 46975111 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 112255745 #
Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 #
ITB inst hits
system.cpu.dtb.inst_misses 0 #
ITB inst misses
system.cpu.dtb.read_hits 0 #
DTB read hits
@@ -64,315 +64,315 @@
system.cpu.itb.misses 0 #
DTB misses
system.cpu.itb.accesses 0 #
DTB accesses
system.cpu.workload.num_syscalls 548 #
Number of system calls
-system.cpu.numCycles 466180431 #
number of cpu cycles simulated
+system.cpu.numCycles 466115086 #
number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
-system.cpu.BPredUnit.lookups 200556895 #
Number of BP lookups
-system.cpu.BPredUnit.condPredicted 157701783 #
Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 13206687 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 107805920 #
Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 98841530 #
Number of BTB hits
+system.cpu.BPredUnit.lookups 200399400 #
Number of BP lookups
+system.cpu.BPredUnit.condPredicted 157559949 #
Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 13227368 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 107557824 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 98829929 #
Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 10112840 #
Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 2450569 #
Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 137282908 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 897241370 #
Number of instructions fetch has processed
-system.cpu.fetch.Branches 200556895 #
Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 108954370 #
Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 197651477 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 54011479 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 89011796 #
Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 101 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1558 #
Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 126941311 #
Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 3919273 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 462356637 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.264737 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.102062 #
Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 10084316 #
Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 2451057 #
Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 137234241 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 896616118 #
Number of instructions fetch has processed
+system.cpu.fetch.Branches 200399400 #
Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 108914245 #
Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 197636410 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 54052361 #
Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 88992455 #
Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 124 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1657 #
Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 126860220 #
Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 3882835 #
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 462293499 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.263975 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.101557 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 264718484 57.25% 57.25% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 16102215 3.48% 60.74% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 21528039 4.66% 65.39% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22972257 4.97% 70.36% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 24519479 5.30% 75.66% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 13176471 2.85% 78.51% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13363017 2.89% 81.40% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 12910820 2.79% 84.20% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 73065855 15.80% 100.00% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 264670388 57.25% 57.25% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 16165090 3.50% 60.75% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 21531844 4.66% 65.41% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22983454 4.97% 70.38% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 24508471 5.30% 75.68% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 13134616 2.84% 78.52% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13371052 2.89% 81.41% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 12920313 2.79% 84.21% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 73008271 15.79% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 462356637 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.430213 #
Number of branch fetches per cycle
-system.cpu.fetch.rate 1.924665 #
Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 152349400 #
Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 84610781 #
Number of cycles decode is blocked
-system.cpu.decode.RunCycles 182515551 #
Number of cycles decode is running
-system.cpu.decode.UnblockCycles 4600527 #
Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 38280378 #
Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 32264539 #
Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 131208 #
Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 977458438 #
Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 310007 #
Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 38280378 #
Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 165802120 #
Number of cycles rename is idle
-system.cpu.rename.BlockCycles 6702227 #
Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 64599197 #
count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 173513863 #
Number of cycles rename is running
-system.cpu.rename.UnblockCycles 13458852 #
Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 899149269 #
Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1570 #
Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2810073 #
Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 7803626 #
Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 65 #
Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1049469958 #
Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3916326628 #
Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3916321968 #
Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4660 #
Number of floating rename lookups
-system.cpu.rename.CommittedMaps 672199888 #
Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 377270070 #
Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 5958245 #
count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 5953011 #
count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 72720727 #
count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 187283500 #
Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 75086036 #
Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 17235466 #
Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 11153184 #
Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 806543834 #
Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 6798395 #
Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 700450406 #
Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1593652 #
Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 237057994 #
Number of squashed instructions iterated over during squash; mainly for
profiling
-system.cpu.iq.iqSquashedOperandsExamined 599635413 #
Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3077315 #
Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 462356637 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.514957 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.708817 #
Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 462293499 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.429935 #
Number of branch fetches per cycle
+system.cpu.fetch.rate 1.923594 #
Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 152295850 #
Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 84600682 #
Number of cycles decode is blocked
+system.cpu.decode.RunCycles 182545472 #
Number of cycles decode is running
+system.cpu.decode.UnblockCycles 4580461 #
Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 38271034 #
Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 32275508 #
Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 160463 #
Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 977106792 #
Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 311018 #
Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 38271034 #
Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 165689191 #
Number of cycles rename is idle
+system.cpu.rename.BlockCycles 6700759 #
Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 64642468 #
count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 173582675 #
Number of cycles rename is running
+system.cpu.rename.UnblockCycles 13407372 #
Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 899108485 #
Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1442 #
Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2810546 #
Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 7739563 #
Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 106 #
Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1049429059 #
Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3915911188 #
Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3915906253 #
Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4935 #
Number of floating rename lookups
+system.cpu.rename.CommittedMaps 672199832 #
Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 377229227 #
Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 5987863 #
count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 5982547 #
count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 72814411 #
count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 187298810 #
Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 75062120 #
Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 17028922 #
Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 10874751 #
Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 806565254 #
Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 6815793 #
Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 700720615 #
Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1613210 #
Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 237113606 #
Number of squashed instructions iterated over during squash; mainly for
profiling
+system.cpu.iq.iqSquashedOperandsExamined 598814504 #
Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3094720 #
Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 462293499 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.515748 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.710183 #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
# Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 192897981 41.72% 41.72% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 75235662 16.27% 57.99% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 69361266 15.00% 72.99% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 61039846 13.20% 86.20% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 35358169 7.65% 93.84% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15549191 3.36% 97.21% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 7530638 1.63% 98.84% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 4060857 0.88% 99.71% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1323027 0.29% 100.00% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 192936549 41.73% 41.73% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 75135766 16.25% 57.99% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 69228865 14.98% 72.96% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 61089071 13.21% 86.18% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 35380643 7.65% 93.83% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15554118 3.36% 97.19% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 7568076 1.64% 98.83% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 4045000 0.87% 99.71% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1355411 0.29% 100.00% #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 462356637 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 462293499 #
Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 463542 4.68% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% #
attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6723177 67.88% 72.56% #
attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2717455 27.44% 100.00% #
attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 467117 4.69% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.69% #
attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6749256 67.80% 72.49% #
attempts to use FU when none available
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