changeset d7ddf3266d46 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d7ddf3266d46
description:
X86: Ensure that the CPUID instruction always writes its outputs.
The CPUID instruction was implemented so that it would only write its
results
if the instruction was successful. This works fine on the simple CPU
where
unwritten registers retain their old values, but on a CPU like O3 with
renaming this is broken. The instruction needs to write the old values
back
into the registers explicitly if they aren't being changed.
diffstat:
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 17 ++++++++++++-----
src/arch/x86/isa/formats/cpuid.isa | 5 +----
2 files changed, 13 insertions(+), 9 deletions(-)
diffs (46 lines):
diff -r 2f84b98634ff -r d7ddf3266d46
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon Jun 04 10:43:08
2012 -0700
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon Jun 04 10:43:09
2012 -0700
@@ -721,12 +721,19 @@
0x1: pop_fs();
0x2: CPUIDInst::CPUID({{
CpuidResult result;
- success = doCpuid(xc->tcBase(), bits(Rax, 31, 0),
+ bool success = doCpuid(xc->tcBase(), bits(Rax, 31, 0),
bits(Rcx, 31, 0), result);
- Rax = result.rax;
- Rbx = result.rbx;
- Rcx = result.rcx;
- Rdx = result.rdx;
+ if (success) {
+ Rax = result.rax;
+ Rbx = result.rbx;
+ Rcx = result.rcx;
+ Rdx = result.rdx;
+ } else {
+ Rax = Rax;
+ Rbx = Rbx;
+ Rcx = Rcx;
+ Rdx = Rdx;
+ }
}});
0x3: Inst::BT(Ev,Gv);
0x4: Inst::SHLD(Ev,Gv,Ib);
diff -r 2f84b98634ff -r d7ddf3266d46 src/arch/x86/isa/formats/cpuid.isa
--- a/src/arch/x86/isa/formats/cpuid.isa Mon Jun 04 10:43:08 2012 -0700
+++ b/src/arch/x86/isa/formats/cpuid.isa Mon Jun 04 10:43:09 2012 -0700
@@ -73,13 +73,10 @@
{
// If the CPUID instruction used a valid function number, this will
// be set to true. Otherwise, the instruction does nothing.
- bool success;
%(op_decl)s;
%(op_rd)s;
%(code)s;
- if (success) {
- %(op_wb)s;
- }
+ %(op_wb)s;
return NoFault;
}
}};
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