changeset ed4378739b6e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ed4378739b6e
description:
ARM: Fix MPIDR and MIDR register implementation.
This change allows designating a system as MP capable or not as some
bootloaders/kernels care that it's set right. You can have a single
processor MP capable system, but you can't have a multi-processor
UP only system. This change also fixes the initialization of the MIDR
register.
diffstat:
src/arch/arm/ArmSystem.py | 1 +
src/arch/arm/isa.cc | 19 ++++++++++++++-----
src/arch/arm/system.cc | 8 +++-----
src/arch/arm/system.hh | 3 +++
4 files changed, 21 insertions(+), 10 deletions(-)
diffs (107 lines):
diff -r af47da518149 -r ed4378739b6e src/arch/arm/ArmSystem.py
--- a/src/arch/arm/ArmSystem.py Tue Jun 05 01:23:10 2012 -0400
+++ b/src/arch/arm/ArmSystem.py Tue Jun 05 01:23:10 2012 -0400
@@ -55,6 +55,7 @@
# 0xc00 Primary part number ("c" or higher implies ARM v7)
# 0x0 Revision
midr_regval = Param.UInt32(0x350fc000, "MIDR value")
+ multi_proc = Param.Bool(True, "Multiprocessor system?")
boot_loader = Param.String("", "File that contains the boot loader code if
any")
gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
diff -r af47da518149 -r ed4378739b6e src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Tue Jun 05 01:23:10 2012 -0400
+++ b/src/arch/arm/isa.cc Tue Jun 05 01:23:10 2012 -0400
@@ -39,6 +39,7 @@
*/
#include "arch/arm/isa.hh"
+#include "arch/arm/system.hh"
#include "cpu/checker/cpu.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
@@ -72,7 +73,7 @@
miscRegs[MISCREG_SCTLR] = sctlr;
miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
- // Preserve MIDR accross reset
+ // Preserve MIDR across reset
miscRegs[MISCREG_MIDR] = midr;
/* Start with an event in the mailbox */
@@ -102,8 +103,6 @@
mvfr1.vfpHalfPrecision = 1;
miscRegs[MISCREG_MVFR1] = mvfr1;
- miscRegs[MISCREG_MPIDR] = 0;
-
// Reset values of PRRR and NMRR are implementation dependent
miscRegs[MISCREG_PRRR] =
@@ -172,6 +171,8 @@
MiscReg
ISA::readMiscReg(int misc_reg, ThreadContext *tc)
{
+ ArmSystem *arm_sys;
+
if (misc_reg == MISCREG_CPSR) {
CPSR cpsr = miscRegs[misc_reg];
PCState pc = tc->pcState();
@@ -185,9 +186,17 @@
switch (misc_reg) {
case MISCREG_MPIDR:
+ arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr());
+ assert(arm_sys);
- return 0x80000000 | // multiprocessor extensions available
- tc->cpuId();
+ if (arm_sys->multiProc) {
+ return 0x80000000 | // multiprocessor extensions available
+ tc->cpuId();
+ } else {
+ return 0x80000000 | // multiprocessor extensions available
+ 0x40000000 | // in up system
+ tc->cpuId();
+ }
break;
case MISCREG_ID_MMFR0:
return 0x03; // VMSAv7 support
diff -r af47da518149 -r ed4378739b6e src/arch/arm/system.cc
--- a/src/arch/arm/system.cc Tue Jun 05 01:23:10 2012 -0400
+++ b/src/arch/arm/system.cc Tue Jun 05 01:23:10 2012 -0400
@@ -53,7 +53,7 @@
using namespace Linux;
ArmSystem::ArmSystem(Params *p)
- : System(p), bootldr(NULL)
+ : System(p), bootldr(NULL), multiProc(p->multi_proc)
{
if (p->boot_loader != "") {
bootldr = createObjectFile(p->boot_loader);
@@ -107,10 +107,8 @@
}
for (int i = 0; i < threadContexts.size(); i++) {
- if (p->midr_regval) {
- threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR,
- p->midr_regval);
- }
+ threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR,
+ p->midr_regval);
}
}
diff -r af47da518149 -r ed4378739b6e src/arch/arm/system.hh
--- a/src/arch/arm/system.hh Tue Jun 05 01:23:10 2012 -0400
+++ b/src/arch/arm/system.hh Tue Jun 05 01:23:10 2012 -0400
@@ -98,6 +98,9 @@
return addr & ~1;
return addr;
}
+
+ /** true if this a multiprocessor system */
+ bool multiProc;
};
#endif
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