changeset cc47e11ccec1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cc47e11ccec1
description:
cpu: Don't init simple and inorder CPUs if they are defered.
initCPU() will be called to initialize switched out CPUs for the simple
and
inorder CPU models. this patch prevents those CPUs from being
initialized
because they should get their state from the active CPU when it is
switched
out.
diffstat:
src/arch/arm/utility.cc | 5 +----
src/cpu/inorder/cpu.cc | 2 +-
src/cpu/simple/atomic.cc | 2 +-
src/cpu/simple/timing.cc | 2 +-
4 files changed, 4 insertions(+), 7 deletions(-)
diffs (59 lines):
diff -r f5ee56466b91 -r cc47e11ccec1 src/arch/arm/utility.cc
--- a/src/arch/arm/utility.cc Tue Jun 05 13:52:30 2012 -0400
+++ b/src/arch/arm/utility.cc Tue Jun 05 14:20:13 2012 -0400
@@ -47,7 +47,6 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/fs_translating_port_proxy.hh"
-#include "params/BaseCPU.hh"
#include "sim/full_system.hh"
namespace ArmISA {
@@ -56,10 +55,8 @@
initCPU(ThreadContext *tc, int cpuId)
{
// Reset CP15?? What does that mean -- ali
-
+
// FPEXC.EN = 0
- if (tc->getCpuPtr()->params()->defer_registration)
- return;
static Fault reset = new Reset;
reset->invoke(tc);
diff -r f5ee56466b91 -r cc47e11ccec1 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Tue Jun 05 13:52:30 2012 -0400
+++ b/src/cpu/inorder/cpu.cc Tue Jun 05 14:20:13 2012 -0400
@@ -792,7 +792,7 @@
thread[tid]->initMemProxies(thread[tid]->getTC());
}
- if (FullSystem) {
+ if (FullSystem && !params()->defer_registration) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId());
diff -r f5ee56466b91 -r cc47e11ccec1 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Tue Jun 05 13:52:30 2012 -0400
+++ b/src/cpu/simple/atomic.cc Tue Jun 05 14:20:13 2012 -0400
@@ -86,7 +86,7 @@
// Initialise the ThreadContext's memory proxies
tcBase()->initMemProxies(tcBase());
- if (FullSystem) {
+ if (FullSystem && !params()->defer_registration) {
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
ThreadContext *tc = threadContexts[i];
diff -r f5ee56466b91 -r cc47e11ccec1 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Tue Jun 05 13:52:30 2012 -0400
+++ b/src/cpu/simple/timing.cc Tue Jun 05 14:20:13 2012 -0400
@@ -68,7 +68,7 @@
// Initialise the ThreadContext's memory proxies
tcBase()->initMemProxies(tcBase());
- if (FullSystem) {
+ if (FullSystem && !params()->defer_registration) {
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
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