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Ship it! Ship It! - Steve Reinhardt On June 18, 2012, 9:09 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1274/ > ----------------------------------------------------------- > > (Updated June 18, 2012, 9:09 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9082:549249e14364 > --------------------------- > Mem: Make SimpleMemory single ported > > This patch changes the simple memory to have a single slave port > rather than a vector port. The simple memory makes no attempts at > modelling the contention between multiple ports, and any such > multiplexing and demultiplexing could be done in a bus (or crossbar) > outside the memory controller. This scenario also matches with the > ongoing work on a SimpleDRAM model, which will be a single-ported > single-channel controller that can be used in conjunction with a bus > (or crossbar) to create a multi-port multi-channel controller. > > There are only very few regressions that make use of the vector port, > and these are all for functional accesses only. To facilitate these > cases, memtest and memtest-ruby have been updated to also have a > "functional" bus to perform the (de)multiplexing of the functional > memory accesses. > > > Diffs > ----- > > configs/example/memtest.py fa77985a87c6 > configs/example/ruby_mem_test.py fa77985a87c6 > src/mem/SimpleMemory.py fa77985a87c6 > src/mem/simple_mem.hh fa77985a87c6 > src/mem/simple_mem.cc fa77985a87c6 > tests/configs/memtest-ruby.py fa77985a87c6 > tests/configs/memtest.py fa77985a87c6 > > Diff: http://reviews.gem5.org/r/1274/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
