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Ship it! Ship It! - Ali Saidi On June 11, 2012, 7:47 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1269/ > ----------------------------------------------------------- > > (Updated June 11, 2012, 7:47 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9076:dd03678d404e > --------------------------- > Port: Align port names in C++ and Python > > This patch is a first step to align the port names used in the Python > world and the C++ world. Ultimately it serves to make the use of > config.json together with output from the simulation easier, including > post-processing of statistics. > > Most notably, the CPU, cache, and bus is addressed in this patch, and > there might be other ports that should be updated accordingly. The > dash name separator has also been replaced with a "." which is what is > used to concatenate the names in python, and a separation is made > between the master and slave port in the bus. > > > Diffs > ----- > > src/cpu/inorder/cpu.hh 35ac3a6f8ee0 > src/cpu/inorder/cpu.cc 35ac3a6f8ee0 > src/cpu/o3/cpu.hh 35ac3a6f8ee0 > src/cpu/simple/atomic.cc 35ac3a6f8ee0 > src/cpu/simple/timing.hh 35ac3a6f8ee0 > src/dev/dma_device.cc 35ac3a6f8ee0 > src/dev/io_device.cc 35ac3a6f8ee0 > src/mem/bridge.cc 35ac3a6f8ee0 > src/mem/cache/cache_impl.hh 35ac3a6f8ee0 > src/mem/coherent_bus.cc 35ac3a6f8ee0 > src/mem/noncoherent_bus.cc 35ac3a6f8ee0 > > Diff: http://reviews.gem5.org/r/1269/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
