changeset 48eeef8a0997 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=48eeef8a0997
description:
Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.
There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
diffstat:
configs/example/memtest.py | 6 +++++-
configs/example/ruby_mem_test.py | 8 ++++++--
src/mem/SimpleMemory.py | 2 +-
src/mem/simple_mem.cc | 29 +++++++----------------------
src/mem/simple_mem.hh | 9 +++++----
tests/configs/memtest-ruby.py | 6 +++++-
tests/configs/memtest.py | 6 +++++-
7 files changed, 34 insertions(+), 32 deletions(-)
diffs (209 lines):
diff -r a8749b39f1f8 -r 48eeef8a0997 configs/example/memtest.py
--- a/configs/example/memtest.py Thu Jul 12 12:56:11 2012 -0400
+++ b/configs/example/memtest.py Thu Jul 12 12:56:13 2012 -0400
@@ -141,6 +141,7 @@
# system simulated
system = System(funcmem = SimpleMemory(in_addr_map = False),
+ funcbus = NoncoherentBus(),
physmem = SimpleMemory(latency = "100ns"))
def make_level(spec, prototypes, attach_obj, attach_port):
@@ -169,10 +170,13 @@
parent.cpu = objs
for t in objs:
t.test = getattr(attach_obj, attach_port)
- t.functional = system.funcmem.port
+ t.functional = system.funcbus.slave
make_level(treespec, prototypes, system.physmem, "port")
+# connect reference memory to funcbus
+system.funcbus.master = system.funcmem.port
+
# -----------------------
# run simulation
# -----------------------
diff -r a8749b39f1f8 -r 48eeef8a0997 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Thu Jul 12 12:56:11 2012 -0400
+++ b/configs/example/ruby_mem_test.py Thu Jul 12 12:56:13 2012 -0400
@@ -107,6 +107,7 @@
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
+ funcbus = NoncoherentBus(),
physmem = SimpleMemory())
if options.num_dmas > 0:
@@ -141,7 +142,7 @@
# Tie the cpu memtester ports to the correct system ports
#
cpu.test = system.ruby._cpu_ruby_ports[i].slave
- cpu.functional = system.funcmem.port
+ cpu.functional = system.funcbus.slave
#
# Since the memtester is incredibly bursty, increase the deadlock
@@ -160,7 +161,10 @@
# Tie the dma memtester ports to the correct functional port
# Note that the test port has already been connected to the dma_sequencer
#
- dma.functional = system.funcmem.port
+ dma.functional = system.funcbus.slave
+
+# connect reference memory to funcbus
+system.funcbus.master = system.funcmem.port
# -----------------------
# run simulation
diff -r a8749b39f1f8 -r 48eeef8a0997 src/mem/SimpleMemory.py
--- a/src/mem/SimpleMemory.py Thu Jul 12 12:56:11 2012 -0400
+++ b/src/mem/SimpleMemory.py Thu Jul 12 12:56:13 2012 -0400
@@ -44,6 +44,6 @@
class SimpleMemory(AbstractMemory):
type = 'SimpleMemory'
- port = VectorSlavePort("Slave ports")
+ port = SlavePort("Slave ports")
latency = Param.Latency('30ns', "Request to response latency")
latency_var = Param.Latency('0ns', "Request to response latency variance")
diff -r a8749b39f1f8 -r 48eeef8a0997 src/mem/simple_mem.cc
--- a/src/mem/simple_mem.cc Thu Jul 12 12:56:11 2012 -0400
+++ b/src/mem/simple_mem.cc Thu Jul 12 12:56:13 2012 -0400
@@ -49,24 +49,17 @@
SimpleMemory::SimpleMemory(const Params* p) :
AbstractMemory(p),
- lat(p->latency), lat_var(p->latency_var)
+ port(name() + ".port", *this), lat(p->latency), lat_var(p->latency_var)
{
- for (size_t i = 0; i < p->port_port_connection_count; ++i) {
- ports.push_back(new MemoryPort(csprintf("%s-port-%d", name(), i),
- *this));
- }
}
void
SimpleMemory::init()
{
- for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end();
- ++p) {
- if (!(*p)->isConnected()) {
- fatal("SimpleMemory port %s is unconnected!\n", (*p)->name());
- } else {
- (*p)->sendRangeChange();
- }
+ // allow unconnected memories as this is used in several ruby
+ // systems at the moment
+ if (port.isConnected()) {
+ port.sendRangeChange();
}
}
@@ -102,22 +95,14 @@
if (if_name != "port") {
return MemObject::getSlavePort(if_name, idx);
} else {
- if (idx >= static_cast<int>(ports.size())) {
- fatal("SimpleMemory::getSlavePort: unknown index %d\n", idx);
- }
-
- return *ports[idx];
+ return port;
}
}
unsigned int
SimpleMemory::drain(Event *de)
{
- int count = 0;
- for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end();
- ++p) {
- count += (*p)->drain(de);
- }
+ int count = port.drain(de);
if (count)
changeState(Draining);
diff -r a8749b39f1f8 -r 48eeef8a0997 src/mem/simple_mem.hh
--- a/src/mem/simple_mem.hh Thu Jul 12 12:56:11 2012 -0400
+++ b/src/mem/simple_mem.hh Thu Jul 12 12:56:13 2012 -0400
@@ -54,9 +54,10 @@
#include "params/SimpleMemory.hh"
/**
- * The simple memory is a basic multi-ported memory with an infinite
- * throughput and a fixed latency, potentially with a variance added
- * to it. It uses a SimpleTimingPort to implement the timing accesses.
+ * The simple memory is a basic single-ported memory controller with
+ * an infinite throughput and a fixed latency, potentially with a
+ * variance added to it. It uses a SimpleTimingPort to implement the
+ * timing accesses.
*/
class SimpleMemory : public AbstractMemory
{
@@ -81,7 +82,7 @@
};
- std::vector<MemoryPort*> ports;
+ MemoryPort port;
Tick lat;
Tick lat_var;
diff -r a8749b39f1f8 -r 48eeef8a0997 tests/configs/memtest-ruby.py
--- a/tests/configs/memtest-ruby.py Thu Jul 12 12:56:11 2012 -0400
+++ b/tests/configs/memtest-ruby.py Thu Jul 12 12:56:13 2012 -0400
@@ -79,6 +79,7 @@
# system simulated
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
+ funcbus = NoncoherentBus(),
physmem = SimpleMemory())
Ruby.create_system(options, system)
@@ -91,7 +92,7 @@
# physmem, respectively
#
cpus[i].test = ruby_port.slave
- cpus[i].functional = system.funcmem.port
+ cpus[i].functional = system.funcbus.slave
#
# Since the memtester is incredibly bursty, increase the deadlock
@@ -105,6 +106,9 @@
#
ruby_port.access_phys_mem = False
+# connect reference memory to funcbus
+system.funcmem.port = system.funcbus.master
+
# -----------------------
# run simulation
# -----------------------
diff -r a8749b39f1f8 -r 48eeef8a0997 tests/configs/memtest.py
--- a/tests/configs/memtest.py Thu Jul 12 12:56:11 2012 -0400
+++ b/tests/configs/memtest.py Thu Jul 12 12:56:13 2012 -0400
@@ -57,6 +57,7 @@
# system simulated
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
+ funcbus = NoncoherentBus(),
physmem = SimpleMemory(),
membus = CoherentBus(clock="500GHz", width=16))
@@ -73,10 +74,13 @@
cpu.l1c = L1(size = '32kB', assoc = 4)
cpu.l1c.cpu_side = cpu.test
cpu.l1c.mem_side = system.toL2Bus.slave
- system.funcmem.port = cpu.functional
+ system.funcbus.slave = cpu.functional
system.system_port = system.membus.slave
+# connect reference memory to funcbus
+system.funcmem.port = system.funcbus.master
+
# connect memory to membus
system.physmem.port = system.membus.master
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