> On Sept. 1, 2012, 4:41 p.m., Andreas Hansson wrote: > > src/arch/arm/isa.cc, line 235 > > <http://reviews.gem5.org/r/1344/diff/5/?file=29386#file29386line235> > > > > I really think we have to find a better way of doing this. String > > matching should, in my opinion, never be used to determine the type of a > > module as it is setting ourselves up for hidden assumptions. > > > > Do you agree? > > Anthony Gutierrez wrote: > I agree. However, there is no current way to determine if we have caches > as far as I can tell. Returning a value other than 0 for the cache-related > fields here, when there are no caches, is wrong. And it affects the behavior > of the kernel at the very least. My previous patch added a cacheline size > param to the CPU model. This solved the problem of getting the line size as > well as determining if we have caches. I can revert this back to that.
I think what you suggest might be the best option at the moment. Ultimately, I am a strong believer of the notion of creating a "CPU" wrapper that contains cores (what is called CPU today) and caches, as already mentioned a few times. Any other ideas? - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1344/#review3382 ----------------------------------------------------------- On Sept. 1, 2012, 10:12 a.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1344/ > ----------------------------------------------------------- > > (Updated Sept. 1, 2012, 10:12 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9182:3377bf0ff708 > --------------------------- > ARM: don't set cache fields of CTR reg if there are no caches > > currently the CTR reg sets its fields based on the block size of > the peer connected to its inst port. in the cache where there are > no caches it doesn't make sense to do so. this patch sets only > the relevant fields of the CTR reg if there are no caches and > leaves the cache-related fields as 0. > > > Diffs > ----- > > src/arch/arm/isa.cc 42807286d6cbaa33b43942d7d15ec34cd5dd5d1d > > Diff: http://reviews.gem5.org/r/1344/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
