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Review request for Default. Description ------- Changeset 9187:08e6df9ca60a --------------------------- AddrRange: Transition from Range<T> to AddrRange This patch takes the final plunge and transitions from the templated Range class to the more specific AddrRange. In doing so it changes the obvious Range<Addr> to AddrRange, and also bumps the range_map to be AddrRangeMap. In addition to the obvious changes, including the removal of redundant includes, this patch also does some house keeping in preparing for the introduction of address interleaving support in the ranges. The Range class is also stripped of all the functionality that is never used. Diffs ----- src/arch/x86/interrupts.cc 42807286d6cb src/base/addr_range.hh PRE-CREATION src/base/addr_range_map.hh PRE-CREATION src/base/inet.hh 42807286d6cb src/base/random.hh 42807286d6cb src/base/range.hh 42807286d6cb src/base/range_map.hh 42807286d6cb src/cpu/simple/base.cc 42807286d6cb src/dev/alpha/backdoor.hh 42807286d6cb src/dev/alpha/tsunami_cchip.hh 42807286d6cb src/dev/alpha/tsunami_io.hh 42807286d6cb src/dev/alpha/tsunami_pchip.hh 42807286d6cb src/dev/arm/a9scu.hh 42807286d6cb src/dev/arm/amba_device.hh 42807286d6cb src/dev/arm/amba_fake.hh 42807286d6cb src/dev/arm/gic.hh 42807286d6cb src/dev/arm/kmi.hh 42807286d6cb src/dev/arm/pl011.hh 42807286d6cb src/dev/arm/pl111.hh 42807286d6cb src/dev/arm/rtc_pl031.hh 42807286d6cb src/dev/arm/rv_ctrl.hh 42807286d6cb src/dev/arm/timer_cpulocal.hh 42807286d6cb src/dev/arm/timer_sp804.hh 42807286d6cb src/dev/baddev.hh 42807286d6cb src/dev/isa_fake.hh 42807286d6cb src/dev/mc146818.hh 42807286d6cb src/dev/mips/malta_cchip.hh 42807286d6cb src/dev/mips/malta_io.hh 42807286d6cb src/dev/mips/malta_pchip.hh 42807286d6cb src/dev/pciconfigall.hh 42807286d6cb src/dev/sparc/dtod.hh 42807286d6cb src/dev/sparc/iob.hh 42807286d6cb src/dev/sparc/mm_disk.hh 42807286d6cb src/dev/uart.hh 42807286d6cb src/dev/uart8250.hh 42807286d6cb src/dev/x86/i82094aa.hh 42807286d6cb src/mem/abstract_mem.hh 42807286d6cb src/mem/abstract_mem.cc 42807286d6cb src/mem/bridge.hh 42807286d6cb src/mem/bridge.cc 42807286d6cb src/mem/bus.hh 42807286d6cb src/mem/bus.cc 42807286d6cb src/mem/cache/cache_impl.hh 42807286d6cb src/mem/physical.hh 42807286d6cb src/mem/physical.cc 42807286d6cb src/mem/port.hh 42807286d6cb src/python/m5/params.py 42807286d6cb src/python/swig/range.i 42807286d6cb src/unittest/rangemaptest.cc 42807286d6cb Diff: http://reviews.gem5.org/r/1390/diff/ Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
