> On Sept. 10, 2012, 10:37 a.m., Ali Saidi wrote: > > Ship It!
Any more feedback before I go ahead and ship this? - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1412/#review3425 ----------------------------------------------------------- On Sept. 10, 2012, 10:31 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1412/ > ----------------------------------------------------------- > > (Updated Sept. 10, 2012, 10:31 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9217:cd43fbf518bb > --------------------------- > DRAM: Introduce SimpleDRAM to capture a high-level controller > > This patch introduces a high-level model of a DRAM controller, with a > basic read/write buffer structure, a selectable and customisable > arbiter, a few address mapping options, and the basic DRAM timing > constraints. The parameters make it possible to turn this model into > any desired DDRx/LPDDRx/WideIOx memory controller. > > The intention is not to be cycle accurate or capture every aspect of a > DDR DRAM interface, but rather to enable exploring of the high-level > knobs with a good simulation speed. Thus, contrary to e.g. DRAMSim > this module emphasizes simulation speed with a good-enough accuracy. > > This module is merely a starting point, and there are plenty additions > and improvements to come. A notable addition is the support for > address-striping in the bus to enable a multi-channel DRAM > controller. Also note that there are still a few "todo's" in the code > base that will be addressed as we go along. > > A follow-up patch will add basic performance regressions that use the > traffic generator to exercise a few well-defined corner cases. > > > Diffs > ----- > > src/mem/SConscript 09d63f1e3559 > src/mem/SimpleDRAM.py PRE-CREATION > src/mem/simple_dram.hh PRE-CREATION > src/mem/simple_dram.cc PRE-CREATION > > Diff: http://reviews.gem5.org/r/1412/diff/ > > > Testing > ------- > > Ran a number of performance regressions and SE/FS > benchmarks. > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
