[gem5-dev] changeset in gem5: Mem: Tidy up bus member variables types

[Andreas Hansson]

changeset 7d506c3ef13d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7d506c3ef13d
description:
        Mem: Tidy up bus member variables types

        This patch merely tidies up the types used for the bus member
        variables. It also makes the constant ones const.

diffstat:

 src/mem/Bus.py |   6 +++---
 src/mem/bus.cc |  10 +---------
 src/mem/bus.hh |  10 +++++-----
 3 files changed, 9 insertions(+), 17 deletions(-)

diffs (65 lines):

diff -r c9f8a432e5ea -r 7d506c3ef13d src/mem/Bus.py
--- a/src/mem/Bus.py    Fri Sep 21 10:11:22 2012 -0400
+++ b/src/mem/Bus.py    Fri Sep 21 10:11:24 2012 -0400
@@ -50,9 +50,9 @@
     # Override the default clock
     clock = '1GHz'
     header_cycles = Param.Cycles(1, "cycles of overhead per transaction")
-    width = Param.Int(8, "bus width (bytes)")
-    block_size = Param.Int(64, "The default block size if not set by " \
-                               "any connected module")
+    width = Param.Unsigned(8, "bus width (bytes)")
+    block_size = Param.Unsigned(64, "The default block size if not set by " \
+                                    "any connected module")
 
     # The default port can be left unconnected, or be used to connect
     # a default slave port
diff -r c9f8a432e5ea -r 7d506c3ef13d src/mem/bus.cc
--- a/src/mem/bus.cc    Fri Sep 21 10:11:22 2012 -0400
+++ b/src/mem/bus.cc    Fri Sep 21 10:11:24 2012 -0400
@@ -61,15 +61,7 @@
       useDefaultRange(p->use_default_range),
       defaultBlockSize(p->block_size),
       cachedBlockSize(0), cachedBlockSizeValid(false)
-{
-    //width, clock period, and header cycles must be positive
-    if (width <= 0)
-        fatal("Bus width must be positive\n");
-    if (clock <= 0)
-        fatal("Bus clock period must be positive\n");
-    if (headerCycles <= 0)
-        fatal("Number of header cycles must be positive\n");
-}
+{}
 
 BaseBus::~BaseBus()
 {
diff -r c9f8a432e5ea -r 7d506c3ef13d src/mem/bus.hh
--- a/src/mem/bus.hh    Fri Sep 21 10:11:22 2012 -0400
+++ b/src/mem/bus.hh    Fri Sep 21 10:11:24 2012 -0400
@@ -228,9 +228,9 @@
     };
 
     /** cycles of overhead per transaction */
-    int headerCycles;
+    const Cycles headerCycles;
     /** the width of the bus in bytes */
-    int width;
+    const uint32_t width;
 
     typedef AddrRangeMap<PortID>::iterator PortMapIter;
     typedef AddrRangeMap<PortID>::const_iterator PortMapConstIter;
@@ -346,10 +346,10 @@
        address not handled by another port and not in default device's
        range will cause a fatal error.  If false, just send all
        addresses not handled by another port to default device. */
-    bool useDefaultRange;
+    const bool useDefaultRange;
 
-    unsigned defaultBlockSize;
-    unsigned cachedBlockSize;
+    const uint32_t defaultBlockSize;
+    uint32_t cachedBlockSize;
     bool cachedBlockSizeValid;
 
     BaseBus(const BaseBusParams *p);
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