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Ship it! Seems fine to me. - Nilay Vaish On Sept. 21, 2012, 9:06 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1433/ > ----------------------------------------------------------- > > (Updated Sept. 21, 2012, 9:06 a.m.) > > > Review request for Default. > > > Description > ------- > > This patch changes the default 1 Tick clock period to a proxy that > resolves the parents clock. As a result of this, the caches and > L1-to-L2 bus, for example, will automatically use the clock period of > the CPU unless explicitly overridden. > > To ensure backwards compatibility, the System class overrides the > proxy and specifies a 1 Tick clock. We could change this to something > more reasonable in a follow-on patch, perhaps 2 GHz or something > similar. > > With this patch applied, all clocked objects should have a reasonable > clock period set, and could start specifying delays in Cycles instead > of absolute time. > > > Diffs > ----- > > src/sim/ClockedObject.py 7d506c3ef13d > src/sim/System.py 7d506c3ef13d > > Diff: http://reviews.gem5.org/r/1433/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
