changeset f1b35c618252 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f1b35c618252 description: sim: Move CPU-specific methods from SimObject to the BaseCPU class
diffstat: src/cpu/BaseCPU.py | 16 ++++++++++++++++ src/cpu/base.hh | 24 +++++++++++++++++++----- src/python/m5/SimObject.py | 5 ----- src/python/m5/simulate.py | 2 +- src/sim/sim_object.cc | 13 ------------- src/sim/sim_object.hh | 23 ----------------------- 6 files changed, 36 insertions(+), 47 deletions(-) diffs (152 lines): diff -r e0d2a8e9f445 -r f1b35c618252 src/cpu/BaseCPU.py --- a/src/cpu/BaseCPU.py Tue Sep 25 11:49:40 2012 -0500 +++ b/src/cpu/BaseCPU.py Tue Sep 25 11:49:40 2012 -0500 @@ -77,6 +77,22 @@ type = 'BaseCPU' abstract = True + @classmethod + def export_method_cxx_predecls(cls, code): + code('#include "cpu/base.hh"') + + + @classmethod + def export_methods(cls, code): + code(''' + void switchOut(); + void takeOverFrom(BaseCPU *cpu); +''') + + def takeOverFrom(self, old_cpu): + self._ccObject.takeOverFrom(old_cpu._ccObject) + + system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") numThreads = Param.Unsigned(1, "number of HW thread contexts") diff -r e0d2a8e9f445 -r f1b35c618252 src/cpu/base.hh --- a/src/cpu/base.hh Tue Sep 25 11:49:40 2012 -0500 +++ b/src/cpu/base.hh Tue Sep 25 11:49:40 2012 -0500 @@ -278,13 +278,27 @@ void registerThreadContexts(); - /// Prepare for another CPU to take over execution. When it is - /// is ready (drained pipe) it signals the sampler. + /** + * Prepare for another CPU to take over execution. + * + * When this method exits, all internal state should have been + * flushed. After the method returns, the simulator calls + * takeOverFrom() on the new CPU with this CPU as its parameter. + */ virtual void switchOut(); - /// Take over execution from the given CPU. Used for warm-up and - /// sampling. - virtual void takeOverFrom(BaseCPU *); + /** + * Load the state of a CPU from the previous CPU object, invoked + * on all new CPUs that are about to be switched in. + * + * A CPU model implementing this method is expected to initialize + * its state from the old CPU and connect its memory (unless they + * are already connected) to the memories connected to the old + * CPU. + * + * @param cpu CPU to initialize read state from. + */ + virtual void takeOverFrom(BaseCPU *cpu); /** * Number of threads we're actually simulating (<= SMT_MAX_THREADS). diff -r e0d2a8e9f445 -r f1b35c618252 src/python/m5/SimObject.py --- a/src/python/m5/SimObject.py Tue Sep 25 11:49:40 2012 -0500 +++ b/src/python/m5/SimObject.py Tue Sep 25 11:49:40 2012 -0500 @@ -602,8 +602,6 @@ unsigned int drain(Event *drain_event); void resume(); - void switchOut(); - void takeOverFrom(BaseCPU *cpu); ''') # Initialize new instance. For objects with SimObject-valued @@ -1050,9 +1048,6 @@ for portRef in self._port_refs.itervalues(): portRef.ccConnect() - def takeOverFrom(self, old_cpu): - self._ccObject.takeOverFrom(old_cpu._ccObject) - # Function to provide to C++ so it can look up instances based on paths def resolveSimObject(name): obj = instanceDict[name] diff -r e0d2a8e9f445 -r f1b35c618252 src/python/m5/simulate.py --- a/src/python/m5/simulate.py Tue Sep 25 11:49:40 2012 -0500 +++ b/src/python/m5/simulate.py Tue Sep 25 11:49:40 2012 -0500 @@ -221,7 +221,7 @@ # Now all of the CPUs are ready to be switched out for old_cpu, new_cpu in cpuList: - old_cpu._ccObject.switchOut() + old_cpu.switchOut() for old_cpu, new_cpu in cpuList: new_cpu.takeOverFrom(old_cpu) diff -r e0d2a8e9f445 -r f1b35c618252 src/sim/sim_object.cc --- a/src/sim/sim_object.cc Tue Sep 25 11:49:40 2012 -0500 +++ b/src/sim/sim_object.cc Tue Sep 25 11:49:40 2012 -0500 @@ -163,19 +163,6 @@ state = Running; } -void -SimObject::switchOut() -{ - panic("Unimplemented!"); -} - -void -SimObject::takeOverFrom(BaseCPU *cpu) -{ - panic("Unimplemented!"); -} - - SimObject * SimObject::find(const char *name) { diff -r e0d2a8e9f445 -r f1b35c618252 src/sim/sim_object.hh --- a/src/sim/sim_object.hh Tue Sep 25 11:49:40 2012 -0500 +++ b/src/sim/sim_object.hh Tue Sep 25 11:49:40 2012 -0500 @@ -255,29 +255,6 @@ */ virtual void resume(); - /** - * Prepare a CPU model to be switched out, invoked on active CPUs - * that are about to be replaced. - * - * @note This should only be implemented in CPU models. - */ - virtual void switchOut(); - - /** - * Load the state of a CPU from the previous CPU object, invoked - * on all new CPUs that are about to be switched in. - * - * A CPU model implementing this method is expected to initialize - * its state from the old CPU and connect its memory (unless they - * are already connected) to the memories connected to the old - * CPU. - * - * @note This should only be implemented in CPU models. - * - * @param cpu CPU to initialize read state from. - */ - virtual void takeOverFrom(BaseCPU *cpu); - #ifdef DEBUG public: bool doDebugBreak; _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev