changeset f610f5942ded in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f610f5942ded
description:
Configs: Set the memtest clock to a reasonable value
This patch changes the memtest clock from 1THz (the default) to 2GHz,
similar to the CPUs in the other regressions. This is useful as the
caches will adopt the same clock as the CPU. The bus clock rate is
scaled accordingly, and the L1-L2 bus is kept at the CPU clock while
the memory bus is at half that frequency.
A separate patch updates the affected stats.
diffstat:
tests/configs/memtest-ruby.py | 2 +-
tests/configs/memtest.py | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diffs (35 lines):
diff -r 9901180cd573 -r f610f5942ded tests/configs/memtest-ruby.py
--- a/tests/configs/memtest-ruby.py Mon Oct 15 08:09:54 2012 -0400
+++ b/tests/configs/memtest-ruby.py Mon Oct 15 08:09:57 2012 -0400
@@ -69,7 +69,7 @@
nb_cores = 8
# ruby does not support atomic, functional, or uncacheable accesses
-cpus = [ MemTest(atomic=False, percent_functional=50,
+cpus = [ MemTest(clock = '2GHz', atomic=False, percent_functional=50,
percent_uncacheable=0, suppress_func_warnings=True) \
for i in xrange(nb_cores) ]
diff -r 9901180cd573 -r f610f5942ded tests/configs/memtest.py
--- a/tests/configs/memtest.py Mon Oct 15 08:09:54 2012 -0400
+++ b/tests/configs/memtest.py Mon Oct 15 08:09:57 2012 -0400
@@ -55,16 +55,16 @@
#MAX CORES IS 8 with the fals sharing method
nb_cores = 8
-cpus = [ MemTest() for i in xrange(nb_cores) ]
+cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(),
- membus = CoherentBus(clock="500GHz", width=16))
+ membus = CoherentBus(clock="1GHz", width=16))
# l2cache & bus
-system.toL2Bus = CoherentBus(clock="500GHz", width=16)
+system.toL2Bus = CoherentBus(clock="2GHz", width=16)
system.l2c = L2(size='64kB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
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