[gem5-dev] changeset in gem5: ruby banked array: do away with event scheduling

[Nilay Vaish]

changeset b6d1e257d488 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b6d1e257d488
description:
        ruby banked array: do away with event scheduling
        It seems unecessary that the BankedArray class needs to schedule an 
event
        to figure out when the access ends. Instead only the time for the end 
of access
        needs to be tracked.

diffstat:

 src/mem/ruby/system/BankedArray.cc |  27 +++++++++++++--------------
 src/mem/ruby/system/BankedArray.hh |  23 +++++++++--------------
 2 files changed, 22 insertions(+), 28 deletions(-)

diffs (102 lines):

diff -r f4ba9a861e65 -r b6d1e257d488 src/mem/ruby/system/BankedArray.cc
--- a/src/mem/ruby/system/BankedArray.cc        Mon Oct 15 17:27:15 2012 -0500
+++ b/src/mem/ruby/system/BankedArray.cc        Mon Oct 15 17:27:15 2012 -0500
@@ -29,15 +29,12 @@
  *
  */
 
-#include <vector>
+#include "base/intmath.hh"
+#include "mem/ruby/system/BankedArray.hh"
+#include "mem/ruby/system/System.hh"
 
-#include "base/intmath.hh"
-#include "mem/ruby/common/TypeDefines.hh"
-#include "mem/ruby/system/BankedArray.hh"
-#include "sim/eventq.hh"
-
-BankedArray::BankedArray(unsigned int banks, Cycles accessLatency, unsigned 
int startIndexBit) :
-    EventManager(&mainEventQueue)
+BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
+                         unsigned int startIndexBit)
 {
     this->banks = banks;
     this->accessLatency = accessLatency;
@@ -59,19 +56,21 @@
     unsigned int bank = mapIndexToBank(idx);
     assert(bank < banks);
 
-    if (busyBanks[bank].scheduled()) {
-        if (!(busyBanks[bank].startAccess == curTick() && busyBanks[bank].idx 
== idx)) {
+    if (busyBanks[bank].endAccess >= curTick()) {
+        if (!(busyBanks[bank].startAccess == curTick() &&
+            busyBanks[bank].idx == idx)) {
             return false;
         } else {
-            return true;  // We tried to allocate resources twice in the same 
cycle for the same addr
+            // We tried to allocate resources twice
+            // in the same cycle for the same addr
+            return true;
         }
     }
 
     busyBanks[bank].idx = idx;
     busyBanks[bank].startAccess = curTick();
-
-    // substract 1 so that next cycle the resource available
-    schedule(busyBanks[bank], curTick()+accessLatency-1);
+    busyBanks[bank].endAccess = curTick() +
+        (accessLatency-1) * g_system_ptr->clockPeriod();
 
     return true;
 }
diff -r f4ba9a861e65 -r b6d1e257d488 src/mem/ruby/system/BankedArray.hh
--- a/src/mem/ruby/system/BankedArray.hh        Mon Oct 15 17:27:15 2012 -0500
+++ b/src/mem/ruby/system/BankedArray.hh        Mon Oct 15 17:27:15 2012 -0500
@@ -35,37 +35,32 @@
 #include <vector>
 
 #include "mem/ruby/common/TypeDefines.hh"
-#include "sim/eventq.hh"
+#include "sim/core.hh"
 
-
-
-class BankedArray : public EventManager
+class BankedArray
 {
-private:
+  private:
     unsigned int banks;
     Cycles accessLatency;
     unsigned int bankBits;
     unsigned int startIndexBit;
 
-    //std::vector<bool> busyBanks;
-
-    class TickEvent : public Event
+    class AccessRecord
     {
-    public:
-        TickEvent() : Event() {}
-        void process() {}
+      public:
+        AccessRecord() : idx(0), startAccess(0), endAccess(0) {}
         Index idx;
         Tick startAccess;
+        Tick endAccess;
     };
-    friend class TickEvent;
 
     // If the tick event is scheduled then the bank is busy
     // otherwise, schedule the event and wait for it to complete
-    std::vector<TickEvent> busyBanks;
+    std::vector<AccessRecord> busyBanks;
 
     unsigned int mapIndexToBank(Index idx);
 
-public:
+  public:
     BankedArray(unsigned int banks, Cycles accessLatency, unsigned int 
startIndexBit);
 
     // Note: We try the access based on the cache index, not the address
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