changeset c2e70a9bc340 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c2e70a9bc340
description:
ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system
for more reliable functional read/write accesses. Only the simple
network
has been augmented as of now. Later on Garnet will also support
functional
accesses.
The patch adds functional access code to all the different types of
messages
that protocols can send around. These messages are functionally accessed
by going through the buffers maintained by the network entities.
The patch also rectifies some of the bugs found in coherence protocols
while
testing the patch.
With this patch applied, functional writes always succeed. But
functional
reads can still fail.
diffstat:
configs/example/ruby_mem_test.py | 1 -
src/mem/protocol/MESI_CMP_directory-L1cache.sm | 5 +
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 5 +
src/mem/protocol/MESI_CMP_directory-dir.sm | 7 +-
src/mem/protocol/MESI_CMP_directory-msg.sm | 53 ++++++++--
src/mem/protocol/MI_example-cache.sm | 5 +
src/mem/protocol/MI_example-dir.sm | 13 +-
src/mem/protocol/MI_example-msg.sm | 44 ++++++++-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 12 ++-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 14 +-
src/mem/protocol/MOESI_CMP_directory-dir.sm | 3 +
src/mem/protocol/MOESI_CMP_directory-msg.sm | 40 +++++++
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 2 +-
src/mem/protocol/MOESI_CMP_token-dir.sm | 1 +
src/mem/protocol/MOESI_CMP_token-msg.sm | 47 ++++++++-
src/mem/protocol/MOESI_hammer-cache.sm | 13 ++-
src/mem/protocol/MOESI_hammer-dir.sm | 27 +++-
src/mem/protocol/MOESI_hammer-msg.sm | 57 ++++++++++
src/mem/protocol/Network_test-msg.sm | 4 +
src/mem/protocol/RubySlicc_Exports.sm | 21 ++-
src/mem/protocol/RubySlicc_MemControl.sm | 8 +
src/mem/ruby/buffers/MessageBuffer.cc | 66 ++++++++++++
src/mem/ruby/buffers/MessageBuffer.hh | 20 ++-
src/mem/ruby/buffers/MessageBufferNode.hh | 1 -
src/mem/ruby/network/Network.hh | 13 ++-
src/mem/ruby/network/simple/PerfectSwitch.cc | 1 -
src/mem/ruby/network/simple/SimpleNetwork.cc | 38 +++++++
src/mem/ruby/network/simple/SimpleNetwork.hh | 3 +
src/mem/ruby/network/simple/Switch.cc | 22 ++++
src/mem/ruby/network/simple/Switch.hh | 3 +
src/mem/ruby/slicc_interface/AbstractController.hh | 10 +
src/mem/ruby/slicc_interface/Message.hh | 12 ++
src/mem/ruby/slicc_interface/NetworkMessage.hh | 1 -
src/mem/ruby/slicc_interface/RubyRequest.cc | 37 +++++++
src/mem/ruby/slicc_interface/RubyRequest.hh | 3 +
src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 57 ++++++++++
src/mem/ruby/system/MemoryControl.cc | 14 --
src/mem/ruby/system/MemoryControl.hh | 10 +-
src/mem/ruby/system/RubyMemoryControl.cc | 88 ++++++++++++++++
src/mem/ruby/system/RubyMemoryControl.hh | 2 +
src/mem/ruby/system/System.cc | 110 +++++++++-----------
src/mem/slicc/ast/TypeDeclAST.py | 3 +
src/mem/slicc/symbols/StateMachine.py | 36 ++++++
src/mem/slicc/symbols/SymbolTable.py | 3 +-
src/mem/slicc/symbols/Type.py | 5 +
45 files changed, 802 insertions(+), 138 deletions(-)
diffs (truncated from 1753 to 300 lines):
diff -r 1e8d01c15a77 -r c2e70a9bc340 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Mon Oct 15 17:27:17 2012 -0500
+++ b/configs/example/ruby_mem_test.py Mon Oct 15 17:51:57 2012 -0500
@@ -43,7 +43,6 @@
# Get paths we might need. It's expected this file is in m5/configs/example.
config_path = os.path.dirname(os.path.abspath(__file__))
config_root = os.path.dirname(config_path)
-m5_root = os.path.dirname(config_root)
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
diff -r 1e8d01c15a77 -r c2e70a9bc340
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Mon Oct 15 17:27:17
2012 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Mon Oct 15 17:51:57
2012 -0500
@@ -201,6 +201,11 @@
}
DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ TBE tbe := L1_TBEs[addr];
+ if(is_valid(tbe)) {
+ return tbe.DataBlk;
+ }
+
return getCacheEntry(addr).DataBlk;
}
diff -r 1e8d01c15a77 -r c2e70a9bc340
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Mon Oct 15 17:27:17
2012 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Mon Oct 15 17:51:57
2012 -0500
@@ -232,6 +232,11 @@
}
DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ TBE tbe := L2_TBEs[addr];
+ if(is_valid(tbe)) {
+ return tbe.DataBlk;
+ }
+
return getCacheEntry(addr).DataBlk;
}
diff -r 1e8d01c15a77 -r c2e70a9bc340 src/mem/protocol/MESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm Mon Oct 15 17:27:17
2012 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm Mon Oct 15 17:51:57
2012 -0500
@@ -110,7 +110,7 @@
void set_tbe(TBE tbe);
void unset_tbe();
void wakeUpBuffers(Address a);
-
+
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
@@ -170,6 +170,11 @@
}
DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ return tbe.DataBlk;
+ }
+
return getDirectoryEntry(addr).DataBlk;
}
diff -r 1e8d01c15a77 -r c2e70a9bc340 src/mem/protocol/MESI_CMP_directory-msg.sm
--- a/src/mem/protocol/MESI_CMP_directory-msg.sm Mon Oct 15 17:27:17
2012 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-msg.sm Mon Oct 15 17:51:57
2012 -0500
@@ -35,11 +35,9 @@
GETS, desc="Get Shared";
GET_INSTR, desc="Get Instruction";
INV, desc="INValidate";
- PUTX, desc="replacement message";
+ PUTX, desc="Replacement message";
WB_ACK, desc="Writeback ack";
- WB_NACK, desc="Writeback neg. ack";
- FWD, desc="Generic FWD";
DMA_READ, desc="DMA Read";
DMA_WRITE, desc="DMA Write";
@@ -47,14 +45,14 @@
// CoherenceResponseType
enumeration(CoherenceResponseType, desc="...") {
- MEMORY_ACK, desc="Ack from memory controller";
- DATA, desc="Data";
- DATA_EXCLUSIVE, desc="Data";
- MEMORY_DATA, desc="Data";
- ACK, desc="Generic invalidate ack";
- WB_ACK, desc="writeback ack";
- UNBLOCK, desc="unblock";
- EXCLUSIVE_UNBLOCK, desc="exclusive unblock";
+ MEMORY_ACK, desc="Ack from memory controller";
+ DATA, desc="Data block for L1 cache in S state";
+ DATA_EXCLUSIVE, desc="Data block for L1 cache in M/E state";
+ MEMORY_DATA, desc="Data block from / to main memory";
+ ACK, desc="Generic invalidate ack";
+ WB_ACK, desc="writeback ack";
+ UNBLOCK, desc="unblock";
+ EXCLUSIVE_UNBLOCK, desc="exclusive unblock";
INV, desc="Invalidate from directory";
}
@@ -70,6 +68,21 @@
int Len;
bool Dirty, default="false", desc="Dirty bit";
PrefetchBit Prefetch, desc="Is this a prefetch request";
+
+ bool functionalRead(Packet *pkt) {
+ // Only PUTX messages contains the data block
+ if (Type == CoherenceRequestType:PUTX) {
+ return testAndRead(Address, DataBlk, pkt);
+ }
+
+ return false;
+ }
+
+ bool functionalWrite(Packet *pkt) {
+ // No check on message type required since the protocol should
+ // read data from those messages that contain the block
+ return testAndWrite(Address, DataBlk, pkt);
+ }
}
// ResponseMsg
@@ -82,4 +95,22 @@
bool Dirty, default="false", desc="Dirty bit";
int AckCount, default="0", desc="number of acks in this message";
MessageSizeType MessageSize, desc="size category of the message";
+
+ bool functionalRead(Packet *pkt) {
+ // Valid data block is only present in message with following types
+ if (Type == CoherenceResponseType:DATA ||
+ Type == CoherenceResponseType:DATA_EXCLUSIVE ||
+ Type == CoherenceResponseType:MEMORY_DATA) {
+
+ return testAndRead(Address, DataBlk, pkt);
+ }
+
+ return false;
+ }
+
+ bool functionalWrite(Packet *pkt) {
+ // No check on message type required since the protocol should
+ // read data from those messages that contain the block
+ return testAndWrite(Address, DataBlk, pkt);
+ }
}
diff -r 1e8d01c15a77 -r c2e70a9bc340 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Mon Oct 15 17:27:17 2012 -0500
+++ b/src/mem/protocol/MI_example-cache.sm Mon Oct 15 17:51:57 2012 -0500
@@ -168,6 +168,11 @@
}
DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ return tbe.DataBlk;
+ }
+
return getCacheEntry(addr).DataBlk;
}
diff -r 1e8d01c15a77 -r c2e70a9bc340 src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm Mon Oct 15 17:27:17 2012 -0500
+++ b/src/mem/protocol/MI_example-dir.sm Mon Oct 15 17:51:57 2012 -0500
@@ -172,6 +172,11 @@
}
DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ return tbe.DataBlk;
+ }
+
return getDirectoryEntry(addr).DataBlk;
}
@@ -506,7 +511,6 @@
out_msg.OriginalRequestorMachId := in_msg.Requestor;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.MessageSize := in_msg.MessageSize;
- //out_msg.Prefetch := in_msg.Prefetch;
DPRINTF(RubySlicc,"%s\n", out_msg);
}
@@ -518,12 +522,8 @@
}
action(w_writeDataToMemoryFromTBE, "\w", desc="Write date to directory
memory from TBE") {
- //getDirectoryEntry(address).DataBlk := TBEs[address].DataBlk;
assert(is_valid(tbe));
- getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk,
- addressOffset(tbe.PhysicalAddress),
- tbe.Len);
-
+ getDirectoryEntry(address).DataBlk := TBEs[address].DataBlk;
}
// TRANSITIONS
@@ -633,7 +633,6 @@
}
transition(M, PUTX, MI) {
- l_writeDataToMemory;
c_clearOwner;
v_allocateTBEFromRequestNet;
l_queueMemoryWBRequest;
diff -r 1e8d01c15a77 -r c2e70a9bc340 src/mem/protocol/MI_example-msg.sm
--- a/src/mem/protocol/MI_example-msg.sm Mon Oct 15 17:27:17 2012 -0500
+++ b/src/mem/protocol/MI_example-msg.sm Mon Oct 15 17:51:57 2012 -0500
@@ -31,11 +31,9 @@
GETX, desc="Get eXclusive";
GETS, desc="Get Shared";
PUTX, desc="Put eXclusive";
- PUTO, desc="Put Owned";
WB_ACK, desc="Writeback ack";
WB_NACK, desc="Writeback neg. ack";
INV, desc="Invalidation";
- FWD, desc="Generic FWD";
}
// CoherenceResponseType
@@ -59,6 +57,20 @@
NetDest Destination, desc="Multicast destination mask";
DataBlock DataBlk, desc="data for the cache line";
MessageSizeType MessageSize, desc="size category of the message";
+
+ bool functionalRead(Packet *pkt) {
+ // Valid data block is only present in PUTX messages
+ if (Type == CoherenceRequestType:PUTX) {
+ return testAndRead(Address, DataBlk, pkt);
+ }
+ return false;
+ }
+
+ bool functionalWrite(Packet *pkt) {
+ // No check on message type required since the protocol should read
+ // data block from only those messages that contain valid data
+ return testAndWrite(Address, DataBlk, pkt);
+ }
}
// ResponseMsg (and also unblock requests)
@@ -70,6 +82,18 @@
DataBlock DataBlk, desc="data for the cache line";
bool Dirty, desc="Is the data dirty (different than
memory)?";
MessageSizeType MessageSize, desc="size category of the message";
+
+ bool functionalRead(Packet *pkt) {
+ // A check on message type should appear here so that only those
+ // messages that contain data
+ return testAndRead(Address, DataBlk, pkt);
+ }
+
+ bool functionalWrite(Packet *pkt) {
+ // No check on message type required since the protocol should read
+ // data block from only those messages that contain valid data
+ return testAndWrite(Address, DataBlk, pkt);
+ }
}
enumeration(DMARequestType, desc="...", default="DMARequestType_NULL") {
@@ -93,6 +117,14 @@
DataBlock DataBlk, desc="DataBlk attached to this request";
int Len, desc="The length of the request";
MessageSizeType MessageSize, desc="size category of the message";
+
+ bool functionalRead(Packet *pkt) {
+ return testAndRead(LineAddress, DataBlk, pkt);
+ }
+
+ bool functionalWrite(Packet *pkt) {
+ return testAndWrite(LineAddress, DataBlk, pkt);
+ }
}
structure(DMAResponseMsg, desc="...", interface="NetworkMessage") {
@@ -102,4 +134,12 @@
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
MessageSizeType MessageSize, desc="size category of the message";
+
+ bool functionalRead(Packet *pkt) {
+ return testAndRead(LineAddress, DataBlk, pkt);
+ }
+
+ bool functionalWrite(Packet *pkt) {
+ return testAndWrite(LineAddress, DataBlk, pkt);
+ }
}
diff -r 1e8d01c15a77 -r c2e70a9bc340
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Mon Oct 15 17:27:17
2012 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Mon Oct 15 17:51:57
2012 -0500
@@ -219,7 +219,17 @@
}
DataBlock getDataBlock(Address addr), return_by_ref="yes" {
- return getCacheEntry(addr).DataBlk;
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