changeset f634a34f2f0b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f634a34f2f0b
description:
stats: Update stats for DMA port send
This patch updates the stats after removing the zero-time send used in
the DMA port.
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 1420 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 2804 ++++-----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 1392 ++--
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 1608 ++--
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 760 +-
5 files changed, 3990 insertions(+), 3994 deletions(-)
diffs (truncated from 9050 to 300 lines):
diff -r 98e05d58f9eb -r f634a34f2f0b
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Tue Oct 23 04:49:33 2012 -0400
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Tue Oct 23 04:49:48 2012 -0400
@@ -1,54 +1,54 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.534230 #
Number of seconds simulated
-sim_ticks 2534229746000 #
Number of ticks simulated
-final_tick 2534229746000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 2.534173 #
Number of seconds simulated
+sim_ticks 2534173219000 #
Number of ticks simulated
+final_tick 2534173219000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 65745 #
Simulator instruction rate (inst/s)
-host_op_rate 84567 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2749446134 #
Simulator tick rate (ticks/s)
-host_mem_usage 380664 #
Number of bytes of host memory used
-host_seconds 921.72 #
Real time elapsed on the host
-sim_insts 60598794 #
Number of instructions simulated
-sim_ops 77947430 #
Number of ops (including micro ops) simulated
+host_inst_rate 58476 #
Simulator instruction rate (inst/s)
+host_op_rate 75217 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2445371941 #
Simulator tick rate (ticks/s)
+host_mem_usage 386340 #
Number of bytes of host memory used
+host_seconds 1036.31 #
Real time elapsed on the host
+sim_insts 60599410 #
Number of instructions simulated
+sim_ops 77948210 #
Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3328 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3520 #
Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 64 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798016 #
Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9095568 #
Number of bytes read from this memory
-system.physmem.bytes_read::total 129434640 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798016 #
Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798016 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3784576 #
Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 798080 #
Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9096016 #
Number of bytes read from this memory
+system.physmem.bytes_read::total 129435344 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 798080 #
Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 798080 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3785216 #
Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 #
Number of bytes written to this memory
-system.physmem.bytes_written::total 6800648 #
Number of bytes written to this memory
+system.physmem.bytes_written::total 6801288 #
Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 52 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 55 #
Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 1 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12469 #
Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142152 #
Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096882 #
Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59134 #
Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12470 #
Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142159 #
Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096893 #
Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59144 #
Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 #
Number of write requests responded to by this memory
-system.physmem.num_writes::total 813152 #
Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47169229 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1313 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813162 #
Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47170281 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1389 #
Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 25 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314895 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589086 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51074548 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314895 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314895 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493383 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190134 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683517 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493383 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47169229 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1313 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314927 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3589343 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51075966 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314927 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314927 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1493669 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190160 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2683829 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1493669 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47170281 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1389 #
Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 25 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314895 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4779219 #
Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53758065 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 314927 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4779503 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53759795 #
Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 64
# Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 #
Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64
# Number of instructions bytes read from this memory
@@ -69,26 +69,26 @@
system.cf0.dma_write_txs 0 #
Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits 0 #
ITB inst hits
system.cpu.checker.dtb.inst_misses 0 #
ITB inst misses
-system.cpu.checker.dtb.read_hits 15049421 #
DTB read hits
-system.cpu.checker.dtb.read_misses 7302 #
DTB read misses
-system.cpu.checker.dtb.write_hits 11294481 #
DTB write hits
+system.cpu.checker.dtb.read_hits 15049590 #
DTB read hits
+system.cpu.checker.dtb.read_misses 7303 #
DTB read misses
+system.cpu.checker.dtb.write_hits 11294593 #
DTB write hits
system.cpu.checker.dtb.write_misses 2189 #
DTB write misses
system.cpu.checker.dtb.flush_tlb 4 #
Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 #
Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 #
Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 6416 #
Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries 6410 #
Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 178 #
Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 #
Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15056723 #
DTB read accesses
-system.cpu.checker.dtb.write_accesses 11296670 #
DTB write accesses
+system.cpu.checker.dtb.read_accesses 15056893 #
DTB read accesses
+system.cpu.checker.dtb.write_accesses 11296782 #
DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 #
ITB inst accesses
-system.cpu.checker.dtb.hits 26343902 #
DTB hits
-system.cpu.checker.dtb.misses 9491 #
DTB misses
-system.cpu.checker.dtb.accesses 26353393 #
DTB accesses
-system.cpu.checker.itb.inst_hits 61777557 #
ITB inst hits
+system.cpu.checker.dtb.hits 26344183 #
DTB hits
+system.cpu.checker.dtb.misses 9492 #
DTB misses
+system.cpu.checker.dtb.accesses 26353675 #
DTB accesses
+system.cpu.checker.itb.inst_hits 61778177 #
ITB inst hits
system.cpu.checker.itb.inst_misses 4471 #
ITB inst misses
system.cpu.checker.itb.read_hits 0 #
DTB read hits
system.cpu.checker.itb.read_misses 0 #
DTB read misses
@@ -105,36 +105,36 @@
system.cpu.checker.itb.perms_faults 0 #
Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 #
DTB read accesses
system.cpu.checker.itb.write_accesses 0 #
DTB write accesses
-system.cpu.checker.itb.inst_accesses 61782028 #
ITB inst accesses
-system.cpu.checker.itb.hits 61777557 #
DTB hits
+system.cpu.checker.itb.inst_accesses 61782648 #
ITB inst accesses
+system.cpu.checker.itb.hits 61778177 #
DTB hits
system.cpu.checker.itb.misses 4471 #
DTB misses
-system.cpu.checker.itb.accesses 61782028 #
DTB accesses
-system.cpu.checker.numCycles 78238000 #
number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61782648 #
DTB accesses
+system.cpu.checker.numCycles 78238784 #
number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 #
number of work items this cpu completed
system.cpu.dtb.inst_hits 0 #
ITB inst hits
system.cpu.dtb.inst_misses 0 #
ITB inst misses
-system.cpu.dtb.read_hits 51729015 #
DTB read hits
-system.cpu.dtb.read_misses 77642 #
DTB read misses
-system.cpu.dtb.write_hits 11810988 #
DTB write hits
-system.cpu.dtb.write_misses 17459 #
DTB write misses
+system.cpu.dtb.read_hits 51719750 #
DTB read hits
+system.cpu.dtb.read_misses 77229 #
DTB read misses
+system.cpu.dtb.write_hits 11809411 #
DTB write hits
+system.cpu.dtb.write_misses 17373 #
DTB write misses
system.cpu.dtb.flush_tlb 4 #
Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 #
Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 #
Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7775 #
Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2642 #
Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 530 #
Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 7767 #
Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2639 #
Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 514 #
Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1366 #
Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51806657 #
DTB read accesses
-system.cpu.dtb.write_accesses 11828447 #
DTB write accesses
+system.cpu.dtb.perms_faults 1315 #
Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51796979 #
DTB read accesses
+system.cpu.dtb.write_accesses 11826784 #
DTB write accesses
system.cpu.dtb.inst_accesses 0 #
ITB inst accesses
-system.cpu.dtb.hits 63540003 #
DTB hits
-system.cpu.dtb.misses 95101 #
DTB misses
-system.cpu.dtb.accesses 63635104 #
DTB accesses
-system.cpu.itb.inst_hits 13083995 #
ITB inst hits
-system.cpu.itb.inst_misses 12083 #
ITB inst misses
+system.cpu.dtb.hits 63529161 #
DTB hits
+system.cpu.dtb.misses 94602 #
DTB misses
+system.cpu.dtb.accesses 63623763 #
DTB accesses
+system.cpu.itb.inst_hits 13045523 #
ITB inst hits
+system.cpu.itb.inst_misses 12142 #
ITB inst misses
system.cpu.itb.read_hits 0 #
DTB read hits
system.cpu.itb.read_misses 0 #
DTB read misses
system.cpu.itb.write_hits 0 #
DTB write hits
@@ -143,121 +143,121 @@
system.cpu.itb.flush_tlb_mva 0 #
Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 #
Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 #
Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5178 #
Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 5168 #
Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 3112 #
Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 3109 #
Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 #
DTB read accesses
system.cpu.itb.write_accesses 0 #
DTB write accesses
-system.cpu.itb.inst_accesses 13096078 #
ITB inst accesses
-system.cpu.itb.hits 13083995 #
DTB hits
-system.cpu.itb.misses 12083 #
DTB misses
-system.cpu.itb.accesses 13096078 #
DTB accesses
-system.cpu.numCycles 475967538 #
number of cpu cycles simulated
+system.cpu.itb.inst_accesses 13057665 #
ITB inst accesses
+system.cpu.itb.hits 13045523 #
DTB hits
+system.cpu.itb.misses 12142 #
DTB misses
+system.cpu.itb.accesses 13057665 #
DTB accesses
+system.cpu.numCycles 475815628 #
number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15172784 #
Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12163693 #
Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 783478 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10392072 #
Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8320250 #
Number of BTB hits
+system.cpu.BPredUnit.lookups 15155227 #
Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12146705 #
Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 783529 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 10394615 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8308125 #
Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1454874 #
Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 82640 #
Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 31374160 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 100930999 #
Number of instructions fetch has processed
-system.cpu.fetch.Branches 15172784 #
Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9775124 #
Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22189039 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5936170 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 131560 #
Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 97680943 #
Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2725 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 99805 #
Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 208737
# Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 364
# Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13080141 #
Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1016234 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6355 #
Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 155765235 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.799529 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.166844 #
Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1454278 #
Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 82490 #
Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 31347726 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 100822937 #
Number of instructions fetch has processed
+system.cpu.fetch.Branches 15155227 #
Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9762403 #
Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22167713 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5923551 #
Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 130252 #
Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 97680521 #
Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2843 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 98238 #
Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 209120
# Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 386
# Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13041690 #
Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1002552 #
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6432 #
Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 155704074 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.799073 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.166371 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 133592933 85.77% 85.77% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1382764 0.89% 86.65% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1755577 1.13% 87.78% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2658359 1.71% 89.49% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2327487 1.49% 90.98% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1136384 0.73% 91.71% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2915896 1.87% 93.58% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 784165 0.50% 94.09% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9211670 5.91% 100.00% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 133553129 85.77% 85.77% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1381799 0.89% 86.66% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1755926 1.13% 87.79% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2652519 1.70% 89.49% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2328486 1.50% 90.99% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1136180 0.73% 91.72% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2905092 1.87% 93.58% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 785179 0.50% 94.09% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9205764 5.91% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 155765235 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031878 #
Number of branch fetches per cycle
-system.cpu.fetch.rate 0.212054 #
Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 33515539 #
Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 97301422 #
Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20013824 #
Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1028268 #
Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3906182 #
Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2022458 #
Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 174763 #
Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 117645711 #
Number of instructions handled by decode
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