Hi, Is this patch not of interest? It basically adds the cache hit/miss ratio to ruby_stats. It's been of use to me when I want to enable certain events to be triggered externally from the protocol files (e.g. prefetch on Miss). If not, I can discard it.
malek On Sun, Oct 7, 2012 at 8:00 PM, Malek Musleh <[email protected]> wrote: > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1467/ > Review request for Default. > By Malek Musleh. > Description > > Changeset 9278:bff77f1550d0 > --------------------------- > Ruby: Add Ruby Stats Hit/Miss Profile Access for Protocols > > This patch adds profiling to the cache Accesses for the ruby directory > protocols. The profileMiss action is modified for all the protocols, > otherwise they would not be compilable. The CacheMemory routine profileMiss() > is not renamed in this patch as I am not sure if that should be done in this > patch or separately. The reason being is that currently all cache accesses > are for some reason refered to as 'misses'. Ruby Stats will need to be > updated. > > Testing: > Ran with command line: ./util/regress > --builds=ALPHA_MESI_CMP_directory,ALPHA_MOESI_CMP_directory --modes=se,fs > --compile-variants=opt. SE mode passes, but for some reason /test/quick/fs > directories are not generated. > > Diffs > > - src/mem/protocol/MESI_CMP_directory-L1cache.sm > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/protocol/MESI_CMP_directory-L2cache.sm > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/protocol/MI_example-cache.sm > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/protocol/MOESI_CMP_directory-L1cache.sm > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/protocol/MOESI_CMP_directory-L2cache.sm > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/protocol/MOESI_CMP_token-L1cache.sm > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/protocol/MOESI_CMP_token-L2cache.sm > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/protocol/MOESI_hammer-cache.sm > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/protocol/RubySlicc_Exports.sm > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/protocol/RubySlicc_Types.sm > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/ruby/profiler/CacheProfiler.hh > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/ruby/profiler/CacheProfiler.cc > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/ruby/system/CacheMemory.hh > (a5ede748a1d97a989e9631aba37afbc43de953ed) > - src/mem/ruby/system/CacheMemory.cc > (a5ede748a1d97a989e9631aba37afbc43de953ed) > > View Diff <http://reviews.gem5.org/r/1467/diff/> > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
