changeset 0ad73254027b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0ad73254027b
description:
dev: Make default clock more reasonable for system and devices
This patch changes the default system clock from 1THz to 1GHz. This
clock is used by all modules that do not override the default (parent
clock), and primarily affects the IO subsystem. Every DMA device uses
its clock to schedule the next transfer, and the change will thus
cause this inter-transfer delay to be longer.
The default clock of the bus is removed, as the clock inherited from
the system provides exactly the same value.
A follow-on patch will bump the stats.
diffstat:
src/mem/Bus.py | 2 --
src/sim/System.py | 9 ++++-----
2 files changed, 4 insertions(+), 7 deletions(-)
diffs (31 lines):
diff -r e05e1b69ebf2 -r 0ad73254027b src/mem/Bus.py
--- a/src/mem/Bus.py Thu Oct 25 13:14:42 2012 -0400
+++ b/src/mem/Bus.py Thu Oct 25 13:14:44 2012 -0400
@@ -47,8 +47,6 @@
abstract = True
slave = VectorSlavePort("vector port for connecting masters")
master = VectorMasterPort("vector port for connecting slaves")
- # Override the default clock
- clock = '1GHz'
header_cycles = Param.Cycles(1, "cycles of overhead per transaction")
width = Param.Unsigned(8, "bus width (bytes)")
block_size = Param.Unsigned(64, "The default block size if not set by " \
diff -r e05e1b69ebf2 -r 0ad73254027b src/sim/System.py
--- a/src/sim/System.py Thu Oct 25 13:14:42 2012 -0400
+++ b/src/sim/System.py Thu Oct 25 13:14:44 2012 -0400
@@ -42,11 +42,10 @@
system_port = MasterPort("System port")
# Override the clock from the ClockedObject which looks at the
- # parent clock by default
- clock = '1t'
- # @todo Either make this value 0 and treat it as an error if it is
- # not overridden, or choose a more sensible value in the range of
- # 1GHz
+ # parent clock by default. The 1 GHz default system clock serves
+ # as a start for the modules that rely on the parent to provide
+ # the clock.
+ clock = '1GHz'
@classmethod
def export_method_cxx_predecls(cls, code):
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