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Ship it! Ship It! - Nilay Vaish On Oct. 24, 2012, 3:07 p.m., Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1510/ > ----------------------------------------------------------- > > (Updated Oct. 24, 2012, 3:07 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9334:2980edcf1264 > --------------------------- > ARM: Make ID registers ISA parameters > > This patch makes the values of ID_ISARx, MIDR, and FPSID configurable > as ISA parameter values. Additionally, setMiscReg now ignores writes > to all of the ID registers. > > Note: This moves the MIDR parameter from ArmSystem to ArmISA for > consistency. > > > Diffs > ----- > > src/arch/arm/ArmISA.py PRE-CREATION > src/arch/arm/ArmSystem.py f634a34f2f0b > src/arch/arm/isa.cc f634a34f2f0b > src/arch/arm/system.cc f634a34f2f0b > > Diff: http://reviews.gem5.org/r/1510/diff/ > > > Testing > ------- > > > Thanks, > > Ali Saidi > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
