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seems fine except that actTIcks could be an stl container and the number of activates per time window could become configurable src/mem/simple_dram.hh <http://reviews.gem5.org/r/1588/#comment3666> stl::list? src/mem/simple_dram.cc <http://reviews.gem5.org/r/1588/#comment3667> with a stl list this could just be actTicks.push_front(0); actTicks.pop_back(); - Ali Saidi On Dec. 6, 2012, 8:37 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1588/ > ----------------------------------------------------------- > > (Updated Dec. 6, 2012, 8:37 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9422:9b598dd35701 > --------------------------- > mem: Add tTAW and tFAW to the SimpleDRAM model > > This patch adds two additional scheduling constraints to the DRAM > controller model, to constrain the activation rate. The two metrics > are mutually exclusive, and map to current DDRx, LPDDRx and WIOx > standards. > > > Diffs > ----- > > src/mem/SimpleDRAM.py 844f9e724343 > src/mem/simple_dram.hh 844f9e724343 > src/mem/simple_dram.cc 844f9e724343 > > Diff: http://reviews.gem5.org/r/1588/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
