changeset ecfd5607d5e9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ecfd5607d5e9
description:
SPARC: Keep a copy of the current ASI in the decoder.
Committed by: Nilay Vaish <[email protected]>
diffstat:
src/arch/sparc/decoder.hh | 12 +++++++++---
src/arch/sparc/isa.cc | 3 +++
src/arch/sparc/process.cc | 2 +-
src/arch/sparc/utility.cc | 2 +-
src/sim/syscall_emul.cc | 2 +-
5 files changed, 15 insertions(+), 6 deletions(-)
diffs (87 lines):
diff -r 227a38f9d98c -r ecfd5607d5e9 src/arch/sparc/decoder.hh
--- a/src/arch/sparc/decoder.hh Fri Jan 04 18:09:35 2013 -0600
+++ b/src/arch/sparc/decoder.hh Fri Jan 04 18:09:45 2013 -0600
@@ -49,9 +49,10 @@
// The extended machine instruction being generated
ExtMachInst emi;
bool instDone;
+ MiscReg asi;
public:
- Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+ Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), asi(0)
{}
ThreadContext *
@@ -86,8 +87,7 @@
// into all the execute functions
if (inst & (1 << 13)) {
emi |= (static_cast<ExtMachInst>(
- tc->readMiscRegNoEffect(MISCREG_ASI))
- << (sizeof(MachInst) * 8));
+ asi << (sizeof(MachInst) * 8)));
} else {
emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
<< (sizeof(MachInst) * 8));
@@ -107,6 +107,12 @@
return instDone;
}
+ void
+ setContext(MiscReg _asi)
+ {
+ asi = _asi;
+ }
+
protected:
/// A cache of decoded instruction objects.
static GenericISA::BasicDecodeCache defaultCache;
diff -r 227a38f9d98c -r ecfd5607d5e9 src/arch/sparc/isa.cc
--- a/src/arch/sparc/isa.cc Fri Jan 04 18:09:35 2013 -0600
+++ b/src/arch/sparc/isa.cc Fri Jan 04 18:09:45 2013 -0600
@@ -549,6 +549,9 @@
MiscReg new_val = val;
switch (miscReg) {
+ case MISCREG_ASI:
+ tc->getDecodePtr()->setContext(val);
+ break;
case MISCREG_STICK:
case MISCREG_TICK:
// stick and tick are same thing on niagra
diff -r 227a38f9d98c -r ecfd5607d5e9 src/arch/sparc/process.cc
--- a/src/arch/sparc/process.cc Fri Jan 04 18:09:35 2013 -0600
+++ b/src/arch/sparc/process.cc Fri Jan 04 18:09:45 2013 -0600
@@ -145,7 +145,7 @@
// Set the trap level to 0
tc->setMiscRegNoEffect(MISCREG_TL, 0);
// Set the ASI register to something fixed
- tc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
+ tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
/*
* T1 specific registers
diff -r 227a38f9d98c -r ecfd5607d5e9 src/arch/sparc/utility.cc
--- a/src/arch/sparc/utility.cc Fri Jan 04 18:09:35 2013 -0600
+++ b/src/arch/sparc/utility.cc Fri Jan 04 18:09:45 2013 -0600
@@ -94,7 +94,7 @@
// src->readMiscRegNoEffect(MISCREG_Y));
// dest->setMiscRegNoEffect(MISCREG_CCR,
// src->readMiscRegNoEffect(MISCREG_CCR));
- dest->setMiscRegNoEffect(MISCREG_ASI,
+ dest->setMiscReg(MISCREG_ASI,
src->readMiscRegNoEffect(MISCREG_ASI));
dest->setMiscRegNoEffect(MISCREG_TICK,
src->readMiscRegNoEffect(MISCREG_TICK));
diff -r 227a38f9d98c -r ecfd5607d5e9 src/sim/syscall_emul.cc
--- a/src/sim/syscall_emul.cc Fri Jan 04 18:09:35 2013 -0600
+++ b/src/sim/syscall_emul.cc Fri Jan 04 18:09:45 2013 -0600
@@ -810,7 +810,7 @@
ctc->setMiscReg(MISCREG_CWP, 0);
ctc->setIntReg(NumIntArchRegs + 7, 0);
ctc->setMiscRegNoEffect(MISCREG_TL, 0);
- ctc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
+ ctc->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
for (int y = 8; y < 32; y++)
ctc->setIntReg(y, tc->readIntReg(y));
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