changeset 36ed6d4654bb in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=36ed6d4654bb
description:
regressions: stats update due to decoder changes
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
| 6 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 12 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
| 2 +
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 27 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
| 2 +
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 336 +-
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
| 264 +-
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
| 24 +-
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
| 264 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
| 1392 ++++-----
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
| 264 +-
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
| 264 +-
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
| 264 +-
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
| 264 +-
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
| 264 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
| 10 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
| 22 +-
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
| 258 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
| 2 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
| 16 +-
21 files changed, 1959 insertions(+), 2012 deletions(-)
diffs (truncated from 4625 to 300 lines):
diff -r 6f294e7a93d1 -r 36ed6d4654bb
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
Fri Jan 04 19:00:45 2013 -0600
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
Fri Jan 04 19:00:48 2013 -0600
@@ -10,7 +10,7 @@
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview
terminal vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8
mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@@ -19,7 +19,7 @@
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
@@ -65,7 +65,7 @@
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
diff -r 6f294e7a93d1 -r 36ed6d4654bb
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Fri Jan 04 19:00:45 2013 -0600
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Fri Jan 04 19:00:48 2013 -0600
@@ -4,11 +4,11 @@
sim_ticks 2523500318000 #
Number of ticks simulated
final_tick 2523500318000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 54734 #
Simulator instruction rate (inst/s)
-host_op_rate 70403 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2279341302 #
Simulator tick rate (ticks/s)
-host_mem_usage 401036 #
Number of bytes of host memory used
-host_seconds 1107.12 #
Real time elapsed on the host
+host_inst_rate 64209 #
Simulator instruction rate (inst/s)
+host_op_rate 82591 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2673913922 #
Simulator tick rate (ticks/s)
+host_mem_usage 441476 #
Number of bytes of host memory used
+host_seconds 943.75 #
Real time elapsed on the host
sim_insts 60596849 #
Number of instructions simulated
sim_ops 77944928 #
Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 #
Number of bytes read from this memory
@@ -584,7 +584,7 @@
system.cpu.int_regfile_writes 87979072 #
number of integer regfile writes
system.cpu.fp_regfile_reads 8318 #
number of floating regfile reads
system.cpu.fp_regfile_writes 2932 #
number of floating regfile writes
-system.cpu.misc_regfile_reads 122823412 #
number of misc regfile reads
+system.cpu.misc_regfile_reads 30426999 #
number of misc regfile reads
system.cpu.misc_regfile_writes 912865 #
number of misc regfile writes
system.cpu.icache.replacements 980837 #
number of replacements
system.cpu.icache.tagsinuse 511.007226 #
Cycle average of tags in use
diff -r 6f294e7a93d1 -r 36ed6d4654bb
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr Fri Jan
04 19:00:45 2013 -0600
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr Fri Jan
04 19:00:48 2013 -0600
@@ -12,6 +12,8 @@
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config
registers and jumping to ThumbEE vectors
+warn: Returning thumbEE disabled for now since we don't support CP14config
registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here
diff -r 6f294e7a93d1 -r 36ed6d4654bb
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Fri Jan 04 19:00:45 2013 -0600
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Fri Jan 04 19:00:48 2013 -0600
@@ -4,11 +4,11 @@
sim_ticks 2593146078000 #
Number of ticks simulated
final_tick 2593146078000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 66425 #
Simulator instruction rate (inst/s)
-host_op_rate 85503 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2731005239 #
Simulator tick rate (ticks/s)
-host_mem_usage 409388 #
Number of bytes of host memory used
-host_seconds 949.52 #
Real time elapsed on the host
+host_inst_rate 77303 #
Simulator instruction rate (inst/s)
+host_op_rate 99505 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3178225665 #
Simulator tick rate (ticks/s)
+host_mem_usage 449664 #
Number of bytes of host memory used
+host_seconds 815.91 #
Real time elapsed on the host
sim_insts 63072130 #
Number of instructions simulated
sim_ops 81187111 #
Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 #
Number of bytes read from this memory
@@ -1007,7 +1007,7 @@
system.cpu0.int_regfile_writes 34853003 #
number of integer regfile writes
system.cpu0.fp_regfile_reads 3246 #
number of floating regfile reads
system.cpu0.fp_regfile_writes 906 #
number of floating regfile writes
-system.cpu0.misc_regfile_reads 46878729 #
number of misc regfile reads
+system.cpu0.misc_regfile_reads 13342715 #
number of misc regfile reads
system.cpu0.misc_regfile_writes 527371 #
number of misc regfile writes
system.cpu0.icache.replacements 399233 #
number of replacements
system.cpu0.icache.tagsinuse 511.592262 #
Cycle average of tags in use
@@ -1577,7 +1577,7 @@
system.cpu1.int_regfile_writes 56596470 #
number of integer regfile writes
system.cpu1.fp_regfile_reads 4905 #
number of floating regfile reads
system.cpu1.fp_regfile_writes 2328 #
number of floating regfile writes
-system.cpu1.misc_regfile_reads 81326805 #
number of misc regfile reads
+system.cpu1.misc_regfile_reads 18962770 #
number of misc regfile reads
system.cpu1.misc_regfile_writes 430176 #
number of misc regfile writes
system.cpu1.icache.replacements 614989 #
number of replacements
system.cpu1.icache.tagsinuse 498.619037 #
Cycle average of tags in use
diff -r 6f294e7a93d1 -r 36ed6d4654bb
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini Fri Jan
04 19:00:45 2013 -0600
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini Fri Jan
04 19:00:48 2013 -0600
@@ -10,7 +10,7 @@
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview
terminal vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8
mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@@ -19,11 +19,12 @@
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.physmem system.realview.nvmem
+midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@@ -64,12 +65,12 @@
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -117,7 +118,6 @@
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -497,23 +497,6 @@
[system.cpu.interrupts]
type=ArmInterrupts
-[system.cpu.isa]
-type=ArmISA
-fpsid=1090793632
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=3
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=4027589137
-id_pfr0=49
-id_pfr1=1
-midr=890224640
-
[system.cpu.itb]
type=ArmTLB
children=walker
diff -r 6f294e7a93d1 -r 36ed6d4654bb
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr Fri Jan
04 19:00:45 2013 -0600
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr Fri Jan
04 19:00:48 2013 -0600
@@ -11,6 +11,8 @@
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config
registers and jumping to ThumbEE vectors
+warn: Returning thumbEE disabled for now since we don't support CP14config
registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
diff -r 6f294e7a93d1 -r 36ed6d4654bb
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Fri Jan
04 19:00:45 2013 -0600
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Fri Jan
04 19:00:48 2013 -0600
@@ -4,11 +4,11 @@
sim_ticks 2523500318000 #
Number of ticks simulated
final_tick 2523500318000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 66325 #
Simulator instruction rate (inst/s)
-host_op_rate 85314 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2762063576 #
Simulator tick rate (ticks/s)
-host_mem_usage 400896 #
Number of bytes of host memory used
-host_seconds 913.63 #
Real time elapsed on the host
+host_inst_rate 76318 #
Simulator instruction rate (inst/s)
+host_op_rate 98167 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3178196363 #
Simulator tick rate (ticks/s)
+host_mem_usage 441472 #
Number of bytes of host memory used
+host_seconds 794.00 #
Real time elapsed on the host
sim_insts 60596849 #
Number of instructions simulated
sim_ops 77944928 #
Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 #
Number of bytes read from this memory
@@ -539,7 +539,7 @@
system.cpu.int_regfile_writes 87979071 #
number of integer regfile writes
system.cpu.fp_regfile_reads 8318 #
number of floating regfile reads
system.cpu.fp_regfile_writes 2932 #
number of floating regfile writes
-system.cpu.misc_regfile_reads 122823412 #
number of misc regfile reads
+system.cpu.misc_regfile_reads 30426999 #
number of misc regfile reads
system.cpu.misc_regfile_writes 912865 #
number of misc regfile writes
system.cpu.icache.replacements 980837 #
number of replacements
system.cpu.icache.tagsinuse 511.007226 #
Cycle average of tags in use
@@ -633,6 +633,168 @@
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf
# average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf
# average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.dcache.replacements 643459 #
number of replacements
+system.cpu.dcache.tagsinuse 511.994224 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 21664123 #
Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 643971 #
Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 33.641457 #
Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 35006000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.994224 #
Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999989 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999989 #
Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 13804735 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13804735 #
number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7290056 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7290056 #
number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491
# number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 280491
# number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 285728
# number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 285728
# number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21094791 #
number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21094791 #
number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21094791 #
number of overall hits
+system.cpu.dcache.overall_hits::total 21094791 #
number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 731455
# number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 731455 #
number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2960577
# number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2960577 #
number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626
# number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13626
# number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 12
# number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 12
# number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3692032 #
number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3692032 #
number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3692032
# number of overall misses
+system.cpu.dcache.overall_misses::total 3692032 #
number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000
# number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 9566755000
# number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226
# number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 105515855226
# number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500
# number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500
# number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000
# number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 192000
# number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 115082610226
# number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 115082610226
# number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 115082610226
# number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 115082610226
# number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14536190
# number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14536190 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10250633
# number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10250633
# number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117
# number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 294117
# number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740
# number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 285740
# number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24786823
# number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24786823 #
number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24786823
# number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24786823 #
number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320
# miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050320
# miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819
# miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.288819
# miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329
# miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329
# miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042
# miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042
# miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.148951
# miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.148951 #
miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.148951
# miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.148951
# miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268
# average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937
# average WriteReq miss latency
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