changeset 877293183bdf in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=877293183bdf
description:
arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.
This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
diffstat:
configs/example/fs.py | 2 +
configs/example/ruby_fs.py | 1 +
configs/example/se.py | 2 +
src/arch/alpha/AlphaISA.py | 43 ++++++++++++++++++++++++
src/arch/alpha/SConscript | 1 +
src/arch/alpha/isa.cc | 20 +++++++++++
src/arch/alpha/isa.hh | 13 +++---
src/arch/arm/ArmISA.py | 43 ++++++++++++++++++++++++
src/arch/arm/SConscript | 1 +
src/arch/arm/isa.cc | 22 ++++++++++++
src/arch/arm/isa.hh | 15 +++----
src/arch/mips/MipsISA.py | 47 ++++++++++++++++++++++++++
src/arch/mips/SConscript | 1 +
src/arch/mips/isa.cc | 20 +++++++++--
src/arch/mips/isa.hh | 11 ++++-
src/arch/power/PowerISA.py | 43 ++++++++++++++++++++++++
src/arch/power/SConscript | 2 +
src/arch/power/isa.cc | 65 +++++++++++++++++++++++++++++++++++++
src/arch/power/isa.hh | 13 ++++--
src/arch/sparc/SConscript | 1 +
src/arch/sparc/SparcISA.py | 43 ++++++++++++++++++++++++
src/arch/sparc/isa.cc | 23 +++++++++++++
src/arch/sparc/isa.hh | 14 +++----
src/arch/x86/SConscript | 1 +
src/arch/x86/X86ISA.py | 43 ++++++++++++++++++++++++
src/arch/x86/isa.cc | 19 ++++++++++
src/arch/x86/isa.hh | 12 +++--
src/cpu/BaseCPU.py | 23 +++++++++++++
src/cpu/base.cc | 5 ++
src/cpu/checker/cpu.cc | 7 ++-
src/cpu/dummy_checker.cc | 1 +
src/cpu/inorder/cpu.cc | 16 +++++---
src/cpu/inorder/cpu.hh | 2 +-
src/cpu/inorder/thread_context.cc | 14 +++---
src/cpu/inorder/thread_context.hh | 4 +-
src/cpu/o3/checker.cc | 1 +
src/cpu/o3/cpu.cc | 12 ++++--
src/cpu/o3/cpu.hh | 2 +-
src/cpu/o3/thread_context_impl.hh | 18 +++++-----
src/cpu/ozone/checker_builder.cc | 1 +
src/cpu/ozone/cpu_builder.cc | 1 +
src/cpu/ozone/simple_cpu_builder.cc | 1 +
src/cpu/simple/base.cc | 5 +-
src/cpu/simple_thread.cc | 17 +++++----
src/cpu/simple_thread.hh | 33 +++++++++---------
tests/run.py | 25 ++++++++++++++
46 files changed, 611 insertions(+), 98 deletions(-)
diffs (truncated from 1673 to 300 lines):
diff -r 55fa95053ee8 -r 877293183bdf configs/example/fs.py
--- a/configs/example/fs.py Mon Jan 07 13:05:33 2013 -0500
+++ b/configs/example/fs.py Mon Jan 07 13:05:35 2013 -0500
@@ -139,6 +139,7 @@
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
+ test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
@@ -155,6 +156,7 @@
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
+ drive_sys.cpu.createThreads()
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
if options.fastmem:
diff -r 55fa95053ee8 -r 877293183bdf configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py Mon Jan 07 13:05:33 2013 -0500
+++ b/configs/example/ruby_fs.py Mon Jan 07 13:05:35 2013 -0500
@@ -103,6 +103,7 @@
#
# Tie the cpu ports to the correct ruby system ports
#
+ cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
diff -r 55fa95053ee8 -r 877293183bdf configs/example/se.py
--- a/configs/example/se.py Mon Jan 07 13:05:33 2013 -0500
+++ b/configs/example/se.py Mon Jan 07 13:05:35 2013 -0500
@@ -180,6 +180,8 @@
if options.checker:
system.cpu[i].addCheckerCpu()
+ system.cpu[i].createThreads()
+
if options.ruby:
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
diff -r 55fa95053ee8 -r 877293183bdf src/arch/alpha/AlphaISA.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/alpha/AlphaISA.py Mon Jan 07 13:05:35 2013 -0500
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class AlphaISA(SimObject):
+ type = 'AlphaISA'
+ cxx_class = 'AlphaISA::ISA'
+ cxx_header = "arch/alpha/isa.hh"
diff -r 55fa95053ee8 -r 877293183bdf src/arch/alpha/SConscript
--- a/src/arch/alpha/SConscript Mon Jan 07 13:05:33 2013 -0500
+++ b/src/arch/alpha/SConscript Mon Jan 07 13:05:35 2013 -0500
@@ -59,6 +59,7 @@
Source('vtophys.cc')
SimObject('AlphaInterrupts.py')
+ SimObject('AlphaISA.py')
SimObject('AlphaSystem.py')
SimObject('AlphaTLB.py')
diff -r 55fa95053ee8 -r 877293183bdf src/arch/alpha/isa.cc
--- a/src/arch/alpha/isa.cc Mon Jan 07 13:05:33 2013 -0500
+++ b/src/arch/alpha/isa.cc Mon Jan 07 13:05:35 2013 -0500
@@ -33,11 +33,25 @@
#include "arch/alpha/isa.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
+#include "params/AlphaISA.hh"
#include "sim/serialize.hh"
namespace AlphaISA
{
+ISA::ISA(Params *p)
+ : SimObject(p)
+{
+ clear();
+ initializeIprTable();
+}
+
+const AlphaISAParams *
+ISA::params() const
+{
+ return dynamic_cast<const Params *>(_params);
+}
+
void
ISA::serialize(EventManager *em, std::ostream &os)
{
@@ -151,3 +165,9 @@
}
}
+
+AlphaISA::ISA *
+AlphaISAParams::create()
+{
+ return new AlphaISA::ISA(this);
+}
diff -r 55fa95053ee8 -r 877293183bdf src/arch/alpha/isa.hh
--- a/src/arch/alpha/isa.hh Mon Jan 07 13:05:33 2013 -0500
+++ b/src/arch/alpha/isa.hh Mon Jan 07 13:05:35 2013 -0500
@@ -38,7 +38,9 @@
#include "arch/alpha/registers.hh"
#include "arch/alpha/types.hh"
#include "base/types.hh"
+#include "sim/sim_object.hh"
+struct AlphaISAParams;
class BaseCPU;
class Checkpoint;
class EventManager;
@@ -46,10 +48,11 @@
namespace AlphaISA
{
- class ISA
+ class ISA : public SimObject
{
public:
typedef uint64_t InternalProcReg;
+ typedef AlphaISAParams Params;
protected:
uint64_t fpcr; // floating point condition codes
@@ -101,11 +104,9 @@
return reg;
}
- ISA()
- {
- clear();
- initializeIprTable();
- }
+ const Params *params() const;
+
+ ISA(Params *p);
};
}
diff -r 55fa95053ee8 -r 877293183bdf src/arch/arm/ArmISA.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/ArmISA.py Mon Jan 07 13:05:35 2013 -0500
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class ArmISA(SimObject):
+ type = 'ArmISA'
+ cxx_class = 'ArmISA::ISA'
+ cxx_header = "arch/arm/isa.hh"
diff -r 55fa95053ee8 -r 877293183bdf src/arch/arm/SConscript
--- a/src/arch/arm/SConscript Mon Jan 07 13:05:33 2013 -0500
+++ b/src/arch/arm/SConscript Mon Jan 07 13:05:35 2013 -0500
@@ -72,6 +72,7 @@
Source('vtophys.cc')
SimObject('ArmInterrupts.py')
+ SimObject('ArmISA.py')
SimObject('ArmNativeTrace.py')
SimObject('ArmSystem.py')
SimObject('ArmTLB.py')
diff -r 55fa95053ee8 -r 877293183bdf src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Mon Jan 07 13:05:33 2013 -0500
+++ b/src/arch/arm/isa.cc Mon Jan 07 13:05:35 2013 -0500
@@ -43,6 +43,7 @@
#include "cpu/checker/cpu.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
+#include "params/ArmISA.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"
@@ -50,6 +51,21 @@
namespace ArmISA
{
+ISA::ISA(Params *p)
+ : SimObject(p)
+{
+ SCTLR sctlr;
+ sctlr = 0;
+ miscRegs[MISCREG_SCTLR_RST] = sctlr;
+ clear();
+}
+
+const ArmISAParams *
+ISA::params() const
+{
+ return dynamic_cast<const Params *>(_params);
+}
+
void
ISA::clear()
{
@@ -641,3 +657,9 @@
}
}
+
+ArmISA::ISA *
+ArmISAParams::create()
+{
+ return new ArmISA::ISA(this);
+}
diff -r 55fa95053ee8 -r 877293183bdf src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Mon Jan 07 13:05:33 2013 -0500
+++ b/src/arch/arm/isa.hh Mon Jan 07 13:05:35 2013 -0500
@@ -47,14 +47,16 @@
#include "arch/arm/tlb.hh"
#include "arch/arm/types.hh"
#include "debug/Checkpoint.hh"
+#include "sim/sim_object.hh"
+struct ArmISAParams;
class ThreadContext;
class Checkpoint;
class EventManager;
namespace ArmISA
{
- class ISA
+ class ISA : public SimObject
{
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