changeset 34d2e8082912 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=34d2e8082912
description:
mem: Remove the IIC replacement policy
The IIC replacement policy seems to be unused and has probably
gathered too much bit rot to be useful. This patch removes the IIC and
its associated cache parameters.
diffstat:
src/mem/cache/BaseCache.py | 7 -
src/mem/cache/builder.cc | 48 +--
src/mem/cache/cache.cc | 8 -
src/mem/cache/tags/SConscript | 7 -
src/mem/cache/tags/iic.cc | 649 ------------------------------------
src/mem/cache/tags/iic.hh | 540 -----------------------------
src/mem/cache/tags/iic_repl/Repl.py | 41 --
src/mem/cache/tags/iic_repl/gen.cc | 207 -----------
src/mem/cache/tags/iic_repl/gen.hh | 234 ------------
src/mem/cache/tags/iic_repl/repl.hh | 117 ------
src/mem/config/cache.hh | 2 +-
11 files changed, 6 insertions(+), 1854 deletions(-)
diffs (truncated from 1957 to 300 lines):
diff -r b43a56850757 -r 34d2e8082912 src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py Mon Jan 07 13:05:39 2013 -0500
+++ b/src/mem/cache/BaseCache.py Mon Jan 07 13:05:39 2013 -0500
@@ -52,21 +52,14 @@
hit_latency = Param.Cycles("The hit latency for this cache")
response_latency = Param.Cycles(
"Additional cache latency for the return path to core on a miss");
- hash_delay = Param.Cycles(1, "time in cycles of hash access")
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")
mshrs = Param.Int("number of MSHRs (max outstanding requests)")
- prioritizeRequests = Param.Bool(False,
- "always service demand misses first")
- repl = Param.Repl(NULL, "replacement policy")
size = Param.MemorySize("capacity in bytes")
forward_snoops = Param.Bool(True,
"forward snoops from mem side to cpu side")
is_top_level = Param.Bool(False, "Is this cache at the top level (e.g.
L1)")
- subblock_size = Param.Int(0,
- "Size of subblock in IIC used for compression")
tgts_per_mshr = Param.Int("max number of accesses per MSHR")
- trace_addr = Param.Addr(0, "address to trace")
two_queue = Param.Bool(False,
"whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers")
diff -r b43a56850757 -r 34d2e8082912 src/mem/cache/builder.cc
--- a/src/mem/cache/builder.cc Mon Jan 07 13:05:39 2013 -0500
+++ b/src/mem/cache/builder.cc Mon Jan 07 13:05:39 2013 -0500
@@ -51,10 +51,6 @@
#include "mem/cache/tags/fa_lru.hh"
#endif
-#if defined(USE_CACHE_IIC)
-#include "mem/cache/tags/iic.hh"
-#endif
-
using namespace std;
@@ -87,50 +83,16 @@
#define BUILD_LRU_CACHE BUILD_CACHE_PANIC("lru cache")
#endif
-#if defined(USE_CACHE_IIC)
-#define BUILD_IIC_CACHE do { \
- IIC *tags = new IIC(iic_params); \
- BUILD_CACHE(IIC, tags); \
- } while (0)
-#else
-#define BUILD_IIC_CACHE BUILD_CACHE_PANIC("iic")
-#endif
-
-#define BUILD_CACHES do { \
- if (repl == NULL) { \
- if (numSets == 1) { \
- BUILD_FALRU_CACHE; \
- } else { \
- BUILD_LRU_CACHE; \
- } \
- } else { \
- BUILD_IIC_CACHE; \
- } \
- } while (0)
-
BaseCache *
BaseCacheParams::create()
{
int numSets = size / (assoc * block_size);
- if (subblock_size == 0) {
- subblock_size = block_size;
+
+ if (numSets == 1) {
+ BUILD_FALRU_CACHE;
+ } else {
+ BUILD_LRU_CACHE;
}
-#if defined(USE_CACHE_IIC)
- // Build IIC params
- IIC::Params iic_params;
- iic_params.size = size;
- iic_params.numSets = numSets;
- iic_params.blkSize = block_size;
- iic_params.assoc = assoc;
- iic_params.hashDelay = hash_delay;
- iic_params.hitLatency = hit_latency;
- iic_params.rp = repl;
- iic_params.subblockSize = subblock_size;
-#else
- const void *repl = NULL;
-#endif
-
- BUILD_CACHES;
return NULL;
}
diff -r b43a56850757 -r 34d2e8082912 src/mem/cache/cache.cc
--- a/src/mem/cache/cache.cc Mon Jan 07 13:05:39 2013 -0500
+++ b/src/mem/cache/cache.cc Mon Jan 07 13:05:39 2013 -0500
@@ -46,10 +46,6 @@
#include "mem/cache/tags/fa_lru.hh"
#endif
-#if defined(USE_CACHE_IIC)
-#include "mem/cache/tags/iic.hh"
-#endif
-
#include "mem/cache/cache_impl.hh"
// Template Instantiations
@@ -60,10 +56,6 @@
template class Cache<FALRU>;
#endif
-#if defined(USE_CACHE_IIC)
-template class Cache<IIC>;
-#endif
-
#if defined(USE_CACHE_LRU)
template class Cache<LRU>;
#endif
diff -r b43a56850757 -r 34d2e8082912 src/mem/cache/tags/SConscript
--- a/src/mem/cache/tags/SConscript Mon Jan 07 13:05:39 2013 -0500
+++ b/src/mem/cache/tags/SConscript Mon Jan 07 13:05:39 2013 -0500
@@ -35,12 +35,5 @@
Source('base.cc')
Source('fa_lru.cc')
-Source('iic.cc')
Source('lru.cc')
Source('cacheset.cc')
-
-SimObject('iic_repl/Repl.py')
-Source('iic_repl/gen.cc')
-
-DebugFlag('IIC')
-DebugFlag('IICMore')
diff -r b43a56850757 -r 34d2e8082912 src/mem/cache/tags/iic.cc
--- a/src/mem/cache/tags/iic.cc Mon Jan 07 13:05:39 2013 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,649 +0,0 @@
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- */
-
-/**
- * @file
- * Definitions of the Indirect Index Cache tagstore.
- */
-
-#include <algorithm>
-#include <cmath>
-#include <string>
-#include <vector>
-
-#include "base/intmath.hh"
-#include "base/trace.hh"
-#include "debug/Cache.hh"
-#include "debug/IIC.hh"
-#include "debug/IICMore.hh"
-#include "mem/cache/tags/iic.hh"
-#include "mem/cache/base.hh"
-#include "sim/core.hh"
-
-using namespace std;
-
-/** Track the number of accesses to each cache set. */
-#define PROFILE_IIC 1
-
-IIC::IIC(IIC::Params ¶ms) :
- hashSets(params.numSets), blkSize(params.blkSize), assoc(params.assoc),
- hitLatency(params.hitLatency), subSize(params.subblockSize),
- numSub(blkSize/subSize),
- trivialSize((floorLog2(params.size/subSize)*numSub)/8),
- tagShift(floorLog2(blkSize)), blkMask(blkSize - 1),
- subShift(floorLog2(subSize)), subMask(numSub - 1),
- hashDelay(params.hashDelay),
- numTags(hashSets * assoc + params.size/blkSize -1),
- numSecondary(params.size/blkSize),
- tagNull(numTags),
- primaryBound(hashSets * assoc)
-{
- // Check parameters
- if (blkSize < 4 || !isPowerOf2(blkSize)) {
- fatal("Block size must be at least 4 and a power of 2");
- }
- if (hashSets <= 0 || !isPowerOf2(hashSets)) {
- fatal("# of hashsets must be non-zero and a power of 2");
- }
- if (assoc <= 0) {
- fatal("associativity must be greater than zero");
- }
- if (hitLatency <= 0) {
- fatal("access latency must be greater than zero");
- }
- if (numSub*subSize != blkSize) {
- fatal("blocksize must be evenly divisible by subblock size");
- }
-
- // debug stuff
- freeSecond = numSecondary;
-
- warmedUp = false;
- warmupBound = params.size/blkSize;
- numBlocks = params.size/subSize;
-
- // Replacement Policy Initialization
- repl = params.rp;
- repl->setIIC(this);
-
- //last_miss_time = 0
-
- // allocate data reference counters
- dataReferenceCount = new int[numBlocks];
- memset(dataReferenceCount, 0, numBlocks*sizeof(int));
-
- // Allocate storage for both internal data and block fast access data.
- // We allocate it as one large chunk to reduce overhead and to make
- // deletion easier.
- unsigned data_index = 0;
- dataStore = new uint8_t[(numBlocks + numTags) * blkSize];
- dataBlks = new uint8_t*[numBlocks];
- for (unsigned i = 0; i < numBlocks; ++i) {
- dataBlks[i] = &dataStore[data_index];
- freeDataBlock(i);
- data_index += subSize;
- }
-
- assert(data_index == numBlocks * subSize);
-
- // allocate and init tag store
- tagStore = new IICTag[numTags];
-
- unsigned blkIndex = 0;
- // allocate and init sets
- sets = new IICSet[hashSets];
- for (unsigned i = 0; i < hashSets; ++i) {
- sets[i].assoc = assoc;
- sets[i].tags = new IICTag*[assoc];
- sets[i].chain_ptr = tagNull;
-
- for (unsigned j = 0; j < assoc; ++j) {
- IICTag *tag = &tagStore[blkIndex++];
- tag->chain_ptr = tagNull;
- tag->data_ptr.resize(numSub);
- tag->size = blkSize;
- tag->trivialData = new uint8_t[trivialSize];
- tag->numData = 0;
- sets[i].tags[j] = tag;
- tag->set = i;
- tag->data = &dataStore[data_index];
- data_index += blkSize;
- }
- }
-
- assert(blkIndex == primaryBound);
-
- for (unsigned i = primaryBound; i < tagNull; i++) {
- tagStore[i].chain_ptr = i+1;
- //setup data ptrs to subblocks
- tagStore[i].data_ptr.resize(numSub);
- tagStore[i].size = blkSize;
- tagStore[i].trivialData = new uint8_t[trivialSize];
- tagStore[i].numData = 0;
- tagStore[i].set = 0;
- tagStore[i].data = &dataStore[data_index];
- data_index += blkSize;
- }
- freelist = primaryBound;
-}
-
-IIC::~IIC()
-{
- delete [] dataReferenceCount;
- delete [] dataStore;
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